Following them properly is for your benefit!
This article is a follow-up to “What’s the trouble with AMRs?” In Compliance Magazine, January 2020.
The purpose of AMR is to warn “customers” who use the semiconductor product that there are physical limits that must not be violated if reliability is to be preserved. Each manufacturer decides how to determine appropriate AMR and how and what to publish on the product datasheet. The “Transient AMR” working group of the Industry Council on ESD Target Levels has submitted their report. The main points are summarized below.
A semiconductor industry survey in 2019 obtained responses from representatives of some 18 different semiconductor manufacturers and 61 different semiconductor “customers”. 97% of manufacturer responses indicated that they expect product reliability to be jeopardized if an electrical AMR is ever violated for any length of time. In general, manufacturers agree with the guidance of IEC standard 60134, which has stated the “hard line” definition of Absolute Maximum Ratings (AMR) since 1961. Nearly half of these responders said they would consider the semiconductor product warranty void for AMR violation if it were known. Manufacturers do not typically publish “transient” AMR information, allowing certain transients to exceed the basic AMR without jeopardizing the reliability. One responder indicated that such transient information is sometimes specified, with the assumption that customers who expose the product to transients are careful to prevent a violation. Manufacturers continue to receive “customer returns” failed units with evidence of electrically induced physical damage, EIPD, that of course wasn’t present when the product originally shipped as a new qualified unit. Many of these returned units are badly damaged, indicating that the electrical overstress (EOS) was well beyond AMR, though the cause remains unknown.
Most “customer” survey respondents indicated that they take datasheet AMR quite seriously, while 13% think of AMR more loosely. Half of the customers indicated that AMR must never be exceeded because physical damage is expected. Another third of the customers think that semiconductor AMR defines the limits beyond which reliability may be jeopardized, a softer but still serious definition. Five customers thought that AMR are standardized limits for semiconductor use and expect that some products have more margin beyond AMR than others. Three customers responded that AMR are just “guidelines”, implying that excessive excursions beyond AMR should be avoided. Some customers indicated that they only intentionally violate AMR if the time beyond AMR is short enough to not cause damage – they want manufacturers to provide applicable limits for transients. Certain customers who are especially concerned about the reliability of their own products ensure that electrical stresses are kept far below AMR. Overall, it seems that more customer education may be necessary before there is a universal understanding that AMR are serious limits.
No discussions of AMR were found in the literature search, though there are many papers and even books on the topic of EOS. AMR are safety limits, not meant to be precise or accurate for a given semiconductor unit. There is no industry standard on how to determine and report electrical AMR. A few examples of product datasheets were found that include transient AMR for permitted overshoot on input pulses.
The working group acknowledges the fact that manufacturers don’t typically characterize products “beyond AMR” because there is no apparent return on investment for this. Products are meant to be operated only within maximum operating limits (MOL), where functionality and reliability are guaranteed. Those customers who request “permission” to exceed AMR for short transients must discuss directly with the manufacturer. The customer may need to provide additional support to justify the characterization and reliability tests involved in developing special AMR for certain transients, keeping in mind that unless you have a method to detect latent damage, there will still be a risk that product reliability can be jeopardized unknowingly.
Figure 1 is a “transients” modification of the EOS and AMR relationship figure of “Understanding Electrical Overstress (EOS)”, JEP174, following the concept that the shorter the pulse, the more power is required to cause EOS and physical damage, jeopardizing reliability.
Semiconductor manufacturers characterize and stress test each element type in an IC to define a safe operating area (SOA) for each stress type. This results in datasheet MOL and the formal reliability expectation. Accelerated life tests for reliability qualification stress the product beyond MOL, going into “region B” of the figure based on the well known mathematical models for each wearout mechanism, but products are not typically stressed to fail. Only ESD and Latch-up are specifically stressed to immediate fail, “region D” of the figure. Establishing datasheet AMR is more about safety margin to help the customers avoid latent damage of “region C”.
Reliability stress testing to establish limits for various types of transient EOS pin by pin would be expensive and time-consuming. But we note that software has been developed for simulating circuit behavior, including robustness or weakness against ESD or EOS pulses in general, pin by pin. Simulation methodology has been demonstrated in the literature to be of great use to semiconductor designers and board and system designers. Simulations during product design can potentially be a means for semiconductor manufacturers to quickly identify weak pins or circuit elements, and also lead to increased confidence and accuracy in determining AMR.
The “Transient AMR” working group recommends that the development of a standard for determining and reporting AMR would be useful in the industry, and a standard may contribute to a reduction in customer returns as awareness increases regarding the seriousness of AMR as reliability limits. A “phase 2” of the Transient AMR project is proposed to include a combination of simulation and physical testing of ICs to seek best practice methods in determining and reporting AMR that could include further detail regarding specific transients of concern to customers. If you have any interest or comments regarding the project, please contact Ashok Alagappan (ashok.alagappan@ ansys.com).
Stevan Hunter, PhD, is a former Member of Technical Staff at ON Semiconductor in Phoenix, Arizona, USA, as Reliability Consulting Engineer, ESD Control Champion and Lean Six Sigma Instructor. Stevan has 42 years’ experience in semiconductor engineering and holds certifications as Lean Six Sigma Blackbelt, Reliability Engineer, and ESD Factory Control Manager. Stevan currently focuses on his university teaching, as Faculty Associate at Arizona State University, BYU-Idaho and University of Maryland CALCE. He is a Senior Member of IEEE and ASQ, and member of IMAPS, SRE, AVS, ASEE and ATD.