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Next to FinFET, How Will ESD Suffer?
Roughly a decade ago, starting at 22nm technology nodes, the transistor architecture changed from planar to FinFET [1-3]. Bulk FinFET (FF) which is a multi-gate transistor built on Si substrate...
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The Relationship Between EMI/EMC and ESD
The 2020 EOS/ESD Symposium in September 2020 featured a new EMC Special Session, held on the Wednesday of the Symposium, organized in cooperation between the EMC Society and EOS/ESD Association,...
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What Exactly is ESD for 3D ICs?
For decades, Moore’s law has been driven by the downscaling of transistor dimensions on silicon. When reaching the ultra-advanced integrated circuit (IC) fabrication technologies in the single-digit nm regime (currently...
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Advances in CMOS Technologies Leading to Lower CDM Target Levels
Can you continue aiming for typical CDM protection levels?IntroductionThe ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size...
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Device Failure From The Initial Current Step Of A CDM Discharge
Editor’s Note: The paper on which this article is based was originally presented at the 40th Annual EOS/ESD Symposium, where it was awarded the Symposium Outstanding Paper in 2019. IntroductionRF interfaces tend to...
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ESD Issues for Flat Panel Displays
Introduction to Flat Panel Displays and the Current State of the ArtElectronic displays have been widely adopted around the world, and information displays have become an essential part of human...
