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Background of ESD Basics and Models
This class introduces the basics of ESD: what it is, why it is a problem, and how to test for it. A basic overview of CDM, HBM, HMM, TLP, and system ESD test methods is also presented.
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Basics of ESD and Latch-up device physics
The primary goal of this class is to determine the ESD Design/Operation window, i.e. the electrical boundary within which an ESD protection will meet both functional and ESD requirements. Relevant electrical parameters leading to the ESD Design Window are specified and reviewed for any class of components. Latch-up basics is also covered.
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ESD circuit-chip design Implementation (with Layout principles) CMOS
This class first provides an overview of prevalent ESD failure modes and the available ESD protection building blocks including diodes and transient-triggered active MOSFET clamps. The concept of an “ideal ESD clamp” is described from the perspective of an IC’s operating and failure voltage levels and the expected ESD current level. The next section discusses application scenarios for IO pad protection, distinguishing between rail-based and pad-based protection methods, and showing how the protected circuitry may participate in an ESD event. Preferred rail clamp and busing schemes for IO pad banks, including embedded analog pad domains, are introduced. The CDM response of an IO pad is used as an example for performing ESD network simulations. The concepts of secondary input protection and cross-domain CDM protection are described. The class continues with discussing the potential IC performance impact of added ESD devices and how to minimize it - a GHz LNA receiver is used as an example. The final section describes potential pitfalls of ESD designs and how to avoid them systematically.
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ESD circuit-chip design implementation (with Layout principles) Mixed-Signal High-Voltage
The primary goal of this class is to review and provide the fundamental design notions of the ESD protection solutions that will satisfy the ESD Design Window to meet both functional and ESD requirements.
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ESD EDA Verification Tools
The verification of ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher-pin counts and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another, across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves, may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the ESDA Technical Report TR18.0-01-14 (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development.
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ESD Compact Models and Simulation
Make designer aware of ESD-specific SPICE simulation tasks, including simulation test benches, setup and model limitations. Align with ESDA WG18 recommendations.
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ESD Latch-up Product Testing Basics
This course will present an basic overview of ESD/latchup product testing and debug. Background on the test models/methods, inputs needed for the test lab for job submissions and some common pitfalls will be reviewed.
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ESD Latchup failures troubleshooting techniques and case studies
This course will give a basic overview of the possible failure analysis techniques to utilize on a product when an ESD or latchup failure or improvement to the product is needed. High level overview of the different types of failure analysis and which one is typically best for which failure will be reviewed.
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ESD Factory Basics for Design Engineers
This course will provide the design engineer with the basic understanding of ESD control for safe handling of ESD sensitive devices. It will give the rationale for the engineer to implement ESD safe handling practices and controls in the engineering characterization lab.
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ESD System Level Basics
Based on the understanding of the interaction between board and IC level protection also using SEED simulations , the circuit designer will be able to optimize the on chip protection for interfaces exposed to residual stress of system level ESD.
