Article, Blog Post
October 1, 2020
FinFETs and Their Impact on ESD Protection Design

For 2020, TSMC is targeting to start mass production of its first 5 nm technology. Also, at this node FinFETs are the transistor architecture of choice. In this article, we will introduce FinFETs and their advantages over planar transistors. We will discuss some of the ESD protection design challenges when designing in a FinFET technology and give an outlook on the successors of FinFET.

What are FinFETs? Why do we need them?

For many years, the technology scaling has followed Moore’s law. In the past, transistors were made with a planar device architecture. Silicon oxide was the dominating gate oxide. During technology scaling, the reduction of the gate-oxide thickness resulted in an increase in the gate leakage current because of quantum-mechanical tunneling. Then people started to wonder if Moore’s Law that guided the technology scaling for generations would come to an end. This gave birth to what is known as FinFET [1]. The features of this device development are explained below.

The introduction of new gate stack materials with a higher dielectric constant than silicon oxide enabled a lower gate leakage current for the same effective oxide thickness. The scaling of the device dimensions also reduces the gate length. The short channel effect occurs if the gate length is comparable to the depletion width of the source/drain junctions. With technology scaling, the short channel effect begins to dominate. It leads to a drain-induced lowering of the barrier, the saturation of carrier velocity, and hot carrier degradation. The introduction of a three-dimensional transistor shape like FinFET provides solutions to these issues.

In a FinFET, the source/drain regions form a fin. The gate wraps around the fin (Figure 1). The three-dimensional gate in FinFETs allows improved three-dimensional control of the transistor channel. A better gate-to-channel coupling results in an ideal sub-threshold slope. The short channel effect reduces significantly. Higher mobility and reduced dopant fluctuations allow faster switching times and higher current densities in the transistors. For the same gate length, FinFET achieves a lower leakage current and power consumption. Most importantly, the processing of a FinFET technology is fully compatible with the conventional bulk CMOS processing. This allows the production of this device architecture at an industrial scale. Since its introduction at the 22 nm node, FinFET technologies have been widely used in various commercial applications ranging from mobile application processors to FPGAs.

What is the impact of FinFET on ESD Protection Design?

There was a common expectation that the introduction of FinFET adds new challenges to the ESD protection design. The further scaling of device dimensions would lead to more device self-heating. This could result in a lower intrinsic ESD robustness and higher on-resistance. The contact scheme in FinFET technologies changes from contact holes to contact trenches. This can have the risk of an increased local current crowding. Finally, the scaling of gate oxides would lead to a decrease of the gate-oxide breakdown voltages during ESD stress. In this part, we discuss how much this is still a concern in currently available FinFET technologies and we will focus on both ESD protection diodes.

Shallow-trench isolated (STI) and gated diodes are available as ESD protection diodes. In FinFET technologies, STI diodes are more robust, with a slightly higher on-resistance (Figure 2a) and a lower capacitance (Figure 2b). In a FinFET technology, the STI is less deep than in planar technologies. Therefore, both diode types turn-on with a similar overshoot voltage during a Charge Device Model (CDM) event [2].

Figure 2: FinFET ESD protection diodes – STI vs. gated: TLP I-V curves (a) and capacitance vs diode length (b)

In FinFET, the contact scheme changes compared to 28 nm planar CMOS technologies. Local interconnects made of contact trenches replace the contact holes. This allows an optimization of the layout for increased ESD robustness. In the first FinFET technologies, the diodes had the same orientation as in planar technologies. An optimized layout allows a regrouping of the fins. The diode orientation rotates by 90 degrees [3] (Figure 3). The conduction path changes from horizontal to vertical. This results in about 20% less on-resistance and a slightly improved ESD robustness. The Transmission Line Pulsing (TLP) I-V data in Figure 3c shows nicely how self-heating reduces in the rotated layout. The TLP I-V curve is less bent towards the voltage axis.

Figure 3: Local interconnect (grey color) layout of STI diodes: conventional, non-rotated layout (a); rotated layout (b) and 100ns TLP I-V curves comparing non-rotated and rotated layout (c)

In ESD protection design, the definition of a suitable design window is an important step. In low-voltage technologies, the upper limit is the breakdown voltage of the gate-oxide (Figure 4). Because of better gate control and less electric field across the gate stack, the breakdown voltage does not decrease in a FinFET compared to the same gate stack in a planar device [4]. This enables ESD protection design solutions that meet the ESD protection targets of the semiconductor industry.

Figure 4: Visualization of an ESD design window with a 100 ns TLP I-V curve of an ESD protection diode

Since their introduction, FinFET technologies have become mature technology options. Consequently, solutions for many ESD-related problems have been developed. For example, RC-triggered supply protection clamps have been developed that meet even system-level requirements [5]. The behavior of drain-extended FinFET under ESD stress has been studied. These types of transistors are used in applications where the drain voltage exceeds the supply voltage [6]. Silicon Controlled Rectifier (SCR) has been optimized to provide a low capacitance and robust CDM solution for the 7 nm node [7].

What will follow FinFET?

The International Roadmap for Devices and Systems (IRDS) shows a prediction of the technology development and introduction for the coming years [8] (Figure 5a). Until the 5 nm node, FinFET are the dominating device architecture for logic circuits. From the 3 nm node, FinFET are replaced by gate-all-around nanowire (GAA NW) FET. GAANW FET consists of vertically stacked lateral nanowires (Figure 5b).

Figure 5: Technology nodes and their year of introduction according to the IRDS roadmap [8] (a) and comparison of the cross-section along the fin/nanowire of GAA NW FET and FinFET (b)

The gate around the nanowires allows improved electrostatic control of the transistor channel and device leakage current [9]. GAA NW FET can be made in a fully CMOS compatible manufacturing process. Recent work shows that ESD protection diodes in a GAA technology provide a similar ESD performance to FinFET technologies [10]. This will enable products to meet the ESD protection targets of the semiconductor industry also at the technology nodes beyond 5 nm.


  1. “How the Father of FinFETs Helped Save Moore’s Law,” IEEE Spectrum, May 2020.
  2. S. Chen et al, “VFTLP Characteristics of ESD Protection Diodes in Advanced Bulk FinFET Technology,” EOS/ESD Symposium 2015
  3. S. Chen et al, “ESD Diodes in Sub-20nm Bulk FinFET Technology Nodes,” IEDM 2014
  4. S. Ramey et al, “Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology,” International Reliability Physics Symposium, 2013
  5. M. Tsai et al, “An On-chip Combo Clamp for Surge and Universal ESD Protection in Bulk FinFET Technology,” EOS/ESD Symposium 2016
  6. B. Kumar et al, “Physical Insights into the ESD behavior of Drain Extended FinFETs,” EOS/ESD Symposium 2017
  7. P.L. Peng et al, “Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology,” EOS/ESD Symposium 2019
  8. International Roadmap for Devices and Systems, 2017
  9. H. Mertens et al, “Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,” VLSI Symposium 2016
  10. S. Chen et al, “ESD diodes in a bulk Si gate-all-around vertically stacked horizontal nanowire technology,” IEDM, 2016

Dr. Mirko Scholz is working at Infineon Technologies AG in Germany as Senior Staff Engineer ESD in central ESD development. Since 2007, he has been an active member of the ESD Association standards working groups on device testing. He co-chaired WG 5.6 from 2014 until 2018 and again since April 2020. In 2019, he joined the steering committee of the EOS/ESD Symposium.