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DD103: An Overview of Integrated Circuit ESD
This three hour tutorial is focused on integrated circuit ESD fundamentals, and is targeted for two audiences: the IC circuit designer who needs knowledge of how ESD can affect IC design, test, handling and system use; and those engineers wishing to be introduced to IC ESD, as a primer to further study.
The tutorial covers the following topics:
• ESD Definitions
• Overview of the ESD Threat and ESD Controlled Workspaces
• ESD Stress Models and Standards
• Introduction to Transmission Line Pulse (TLP) ESD Testing
• ESD Design Window
• ESD Protection Network Design
• Power Clamp ESD Design and Tradeoffs
• Input Protection ESD Design
• Output Drivers ESD Design
• Switches (Transmission Gates) ESD Design
• RF ESD Protection
• IC ESD - Integration Issues
• CDM Protection Guidelines
• ESD Design Verification
• ESD Debug and Diagnosis
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DD110: ESD From Basics to Advanced Protection Design
This course gives a comprehensive overview from ESD basics to ESD on-chip design principles, covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality. The attendee will have an in-depth understanding of the principles of ESD device design along with a full perception of what it takes to address almost every kind of design scenario, how to apply rules of thumb for successful on-chip design, knowledge of lessons learned from case studies, and empowerment to communicate with customers on ESD quality issues. In its complete ESD overview, the course offers emphasis on on-chip protection methods including an understanding of any interactions to the eventual system protection.
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DT100: HBM Testing Essentials
This tutorial addresses the details of human body model (HBM) qualification testing. This course will help in the interpretation of the HBM joint standard JEDEC/ANSI/ESDA JS-001 and will include details on waveform verification, understanding of Table 2A (minimum required set of pin combinations) and Table 2B (legacy pin combinations), pin categorization and pin grouping, and I/O pin sampling. Stress plan details will be discussed including efficient testing (reduction in pin count) and some debugging options.
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DT200: CDM Testing Essentials
This tutorial will give students the fundamental information required to quickly learn the CDM testing method on commercial CDM test equipment and the associated oscilloscope/metrology chain information needed to capture and interpret CDM waveforms. Additional information on CDM testing standards and their hardware differences, package effects on the CDM waveforms, and package limitations will be covered. Students will also be introduced to the background information needed in understanding CDM failure modes along with test program output failure types needed to understand the effects of CDM testing.
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DT201: Latch-up Testing and Troubleshooting
This tutorial focuses on latch-up testing and troubleshooting. Latch-up is a failure mechanism primarily seen in CMOS and BiCMOS technologies but can be present in bipolar technologies. During process development, resistance to latch-up is generally characterized and design rules are implemented at device circuit block layout. Design checks for latch-up are often implemented, but latch-up immunity is generally guaranteed by testing. This tutorial will help the student understand the issues related to latch-up testing, ways to prevent latch-up and methods used to verify latch-up resistance in products using the Latch-up Standard, JESD78, test method.
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DT142: Fundamentals of Failure Analysis
Failure analysis is the diagnostic tool of the semiconductor industry. It is the semiconductor equivalent of forensic science. Failure analysis unravels the mystery behind how and why a part failed, determining the root cause and corrective actions needed to prevent future failures. This tutorial is targeted toward people doing stress testing on a daily basis where failures are generated and need to be analyzed to determine what failed and how to improve a part’s robustness. The focus will be on failure analysis methods and tools used to analyze failures resulting from ESD, TLP, or latchup related stressing but will be applicable for wear out as well as infant mortality-related failures as well. The tutorial will cover the five basic steps necessary to perform a failure analysis:
1) Information Gathering,
2) Failure Verification,
3) Failure Site Localization,
4) Root Cause Investigation, and
5) Corrective Action.
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DT210: TLP Fundamentals – Understanding the Equipment Options and IV Data
This tutorial explains what transmission line pulsing (TLP) is and how it can be used for ESD design and development. Taking accurate TLP measurements is important; thus, how TLP systems make measurements and produce IV plots will be reviewed. The IV plots provide very valuable device parameters that are key to understanding the DUT being stressed. The tutorial also explains the parameters extracted from those IV curves. Finally, typical equipment used in TLP systems is reviewed.The tutorial will also explain the parameters that can be extracted from those IV curves. Finally, typical equipment used in TLP systems will be reviewed.
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DD134: Fundamentals of ESD System Level
This tutorial is intended to help those tasked with designing and testing prod-ucts to system-level ESD standards by providing first an overview of what the real-world system ESD threats are and the associated standards that describe these events. Then detailed information on qualification testing is given on IEC 61000-4-2, the most widely used standard, but also ISO 10605 and other standards. This topic includes waveform verification, discharge points, test levels and result classification. System level characterization is broken into five different types including, testing of components outside a system, cable discharge events, charge board events, electro-magnetic field scanning and SEED – system efficient ESD design. The last part of the course dives into the design and simulation strategies for system level robustness where on-board and on-chip protection need to work together. The more popular components for on-board protection are presented and compared.
