Article, Blog Post
July 1, 2021
Next to FinFET, How Will ESD Suffer?

Roughly a decade ago, starting at 22nm technology nodes, the transistor architecture changed from planar to FinFET [1-3]. Bulk FinFET (FF) which is a multi-gate transistor built on Si substrate has been the mainstream in the state-of-the-art logic CMOS technologies for many mobile SoC applications [1-3]. Fortunately, ESD reliability has not been an obstacle in the FinFET era from 22nm to 5nm technology nodes. Nowadays, with the increased requirements of high-performance computing applications, logic CMOS technologies need further evolutions. Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.

New GAA Transistor Architecture

Next to bulk FinFET technologies beyond 5nm nodes, bulk gate-all-around (GAA) technology has been proposed as a promising candidate because of improved channel electrostatic and leakage control [4-8]. The vertically stacked horizontal nanosheets (NS) can further maximize the driving current per layout footprint [8-11]. Compared with nanowires (NW), the NS can provide more driving capability per layout footprint due to the larger effective channel width (Weff) [10, 11], as shown in Figure 1.

Figure 1: 3D schematic images of Gate-all-around (GAA) FETs with two different vertically stacked horizontal nano-architectures: one is the nanowire (NWs) and the other is the nanosheet (NS). Corresponding TEM cross-section views of these different two vertically stacked horizontal GAA NW and GAA NS are shown. Effective work function (EWF) and Tungsten (W) gate metals are also shown [7, 9, 11].

In addition to the new GAA transistor architecture, the integration of a Source/Drain (S/D) dual epitaxy process with strain engineering [3, 12-15] has been proposed to continuously enable better, faster, and more compact devices [13]. For example, in p-type MOSFETs, the Si S/D epitaxy structure is replaced by a SiGe S/D epitaxy structure [13-15] for providing the channel strain engineering. These examples of architecture and material options can bring critical challenges of ESD reliability.

One measure of ESD performance in these new device structures is to characterize diodes as a way of assessing their impact. Prior research has shown the investigations of ESD diodes in SOI and bulk FinFET technologies [16, 17]. ESD diodes in bulk Si GAA vertically-stacked horizontal nanowires (NW) technology have been also reported [18]. In addition, the impact of the material options with SiGe S/D epitaxy on the bulk FF ESD diode performance has also been shown [15, 19]. In this article, the influence of the SiGe epitaxy stressor on bulk GAA NS ESD diodes will be disclosed.

Impacts of NS and SiGe Epitaxy on ESD Diode Performance

Although the NS diodes have enlarged fin dimensions, they did not show any significant advantage on 100ns TLP IV characteristics, as shown in Figure 2 [20]. The wider fin structure in the GAA NS technology can prevent the current crowding inside the fin which should be beneficial to the It2 enhancement. However, the It2 results are relatively similar in these three different advanced CMOS technologies. Moreover, the NS ESD diode even has a higher Ron, compared to the NW ESD diode. The reason can be related to the differences in S/D epitaxy process options. This is not only due to the fin-to-wire or wire-to-sheet architecture differences, but also the S/D (or anode/cathode) epitaxy differences. It is important to note that the S/D (or anode/cathode) regions will still retain a “fin-shape” structure in GAA technology nodes.

Figure 2: Measured TLP IV curves of the ESD diodes in three different technologies. They are bulk FF, bulk GAA NWs, and bulk GAA NS, respectively. The ESD diodes have exactly the same layout parameters [20].

One outcome in the architecture change from FF to GAA NW, due to a different fin height (Hfin) in these two technologies, is that the ESD diodes have different thermal behaviors. A taller fin structure usually has a large epitaxial volume on the anode and cathode regions [18]. This improves the thermal dissipation and results in less self-heating and lower Ron under 100ns TLP stress. However, this taller fin architecture with a reduced fin pitch can result in a smaller contact area at the S/D regions due to the S/D epitaxy growth and the middle-of-line (MOL) process modules, which can impact ESD diode failure levels, as illustrated in Figure 3. With a Hfin of 50nm and a fin pitch (Pfin) of 45nm, the S/D epitaxy growth between any two fins results in their adjacent epitaxy regions merging. This allows an increased area of the contact scheme in MOL local interconnect (LI) processes, as shown in Figure 3a. The contact scheme depth (Dcon) is defined by the top of a Silicon (Si) epitaxy structure and the bottom of a LI recess ending depth in ILD0 layer. With a reduced Pfin of 30nm, the Si epitaxy structure between two fins will be merged, resulting in a reduced contact depth (D’con), as shown in Figure 3b. Taller fins with a further reduced Pfin will have more merged epitaxy volume. The contact scheme along the fin length has been shown to impact It2 [17]. The reduced Dcon can be expected to bring a negative impact on ESD diode performance, increasing its thermal heating under ESD and hence lower failure current. Fortunately, the original fin pitch in sub-5nm GAA NS technology can be relaxed from the industrial 7nm/5nm FF technologies [10]. Therefore, the impact of S/D material options on ESD diode performance can be more critical in GAA NS technologies.

Figure 3: Schematic cross-sectional views at the S/D (or anode/cathode) regions with a fixed Hfin of 50nm but two different fin pitches (Pfin) of (a) 45nm and (b) 30nm. (b) Due to a further merged epitaxy structure, the contact depth (Dcon) is reduced to a shallower contact depth (D’con) between two fins in the ESD diode with the Pfin of 30nm [18].

Different from the GAA NW diodes with their HDD-implanted Si epitaxy in both anode and cathode regions, the GAA NS diodes have the in-situ Boron doped SiGe (SiGe:B) epitaxy anode with a thin Si:B liner and the in-situ Phosphorus doped Si (Si:P) epitaxy cathode. The in-situ Boron doped Si (Si:B) liner is used to prevent the S/D SiGe:B epitaxy structures from being accidentally attacked by the SiGe etchant during the SiGe sacrificial layers etching process (which is needed for releasing the stacked NS structures). This Si:B liner further brings an additional benefit to ESD diodes, as presented in [15, 19, 20]. However, this Si:B liner might be removed in future GAA NS technologies with inner spacer process options. Moreover, the SiGe epitaxy anode of the GAA NS ESD diode can degrade the local thermal dissipation, which can deteriorate the ESD diode performance, for example resulting in its increased Ron, as shown in Figure 2. The S/D process options in next-generation transistors become more crucial to ESD diode performance in future technology nodes.

Upcoming ESD Challenges in DTCO and even STCO Scaling Era

Recently, an improved GAA transistor implementing a fork-shaped architecture has been proposed to further reduce the spacing between the p-type and n-type MOSFETs in a standard cell design, as shown in Figure 4 [21, 22]. Thanks to this minimized n-to-p spacing, the novel fork-sheet (FS) device architecture can offer superior area and performance scalability over the NS architecture [21]. In addition to the promising GAA FS technology, the complementary FET (CFET) which consists of “folding” the n-type MOSFET on top of the p-type MOSFET can provide a high level of scalability by fully eliminating the n-to-p separation bottleneck, as presented in Figure 4. It can reduce the standard cell active area footprint by ~50%. More design-technology co-optimization (DTCO) scaling options, such as buried power rail (BPR) and back-side power delivery network (BS-PDN), have been also proposed as scaling boosters in future logic CMOS technologies [21]. However, ESD reliability has not yet been evaluated, and building efficient ESD protection devices may be challenging for these DCTO scaling options.

Figure 4: Design-technology co-optimization (DTCO) scaling options with various transistor architectures are proposed to obtain the full benefits of transistor scaling at the cell level [21].

Finally, the concept of system-technology-co-optimization (STCO) has been proposed. It can further enhance not only the (sub-)system functional performance but also can increase the diversities of functionality by hetero-system 3D integrations. However, due to the placement of these novel ESD protection strategies in these architectures, the present methodologies described in ESDA component-level testing standards do not describe a process to verify ESD requirements for interconnects in the STCO scaling era of nano-scale die-to-die, die-to-wafer, or wafer-to-wafer 3D stacking options. The EOS/ESD Association Standards Working Groups have been well aware and are working with the industry to better describe the upcoming requirements and techniques of ESD verification for the STCO scaling option with its 3D multi-chip stacking technologies.


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