Workshop Session A: Tuesday September 12th
5:30 p.m. - 7:00 p.m. (Parallel Sessions)
A.1 Friendly ESD Integration of 3rd Party IP in SoCs?
Moderators: Fabrice Blanc, ARM; Peter De Jong, Synopsys, Inc.; James Miller, NXP Semiconductors
More and more 3rd party IP are used to accelerate large SoCs creation, therefore ESD-robust SoCs implementation can’t be controlled anymore by only one ESD specialist and obviously becomes a joint effort and responsibility for the SoC-level designer and the IP providers. Indeed, the success in this IP integration task strongly relies on passing all the required information and aligning on some common ESD assumptions between the IP provider and the SoC designer:
- The key IP design targets and assumptions for ESD & LU
- Some IP ESD protection network details
- The IP integration rules at SoC level
- Some IP silicon validation details
- ESD EDA checks enabled for the IP verification on SoC
A few EDA-ESD tools may come into the loop to help, but no mainstream EDA solution enforces a full comprehensive solution. Come to share your expectations and your experience (good or bad) about SoC implementation with 3rd party IP and ESD-EDA tools. This would be of great value to improve methodology and support for ESD-robust IP integration.
EOS, while equally as important as ESD, has not had the systematic attention throughout the industry in the last few decades. From 2013 through 2016, the Industry Council conducted a massive study to clearly establish the nature of EOS and to offer, through examples and case studies, some of the common causes for unintended EOS damage. The major challenge from the start was to meaningfully survey the existing understanding of EOS experiences prior to the publication of White Paper 4, and to provide a more universal definition of what is EOS, the myriad of root causes that often lead to EOS damage, and the practical methods to mitigate EOS. This workshop aims to bring forth this valuable information and ask the participants what the industry has learned from this document and how to achieve a more widespread communication about EOS to prevent much of the unnecessary EOS damage that routinely causes tension between the supplier and the customer. The audience members are encouraged to bring their own examples of EOS observations that could be discussed as part of the global EOS challenge.
ANSI/ESD S20.20-2014 provides specific requirements for the control of electrostatic discharges greater than or equal to 100 volts HBM, 200 volts CDM, and 35 volts on isolated conductors, which is the basis for an effective ESD control program. ANSI/ESD S20.20 has a caveat that states, "Activities that handle items that are susceptible to lower withstand voltages may require additional control elements or adjusted limits". What should we consider when adding new control elements or adjusting the existing limits?
Additionally, ANSI/ESD S20.20 does not address the processing of high reliability products. For example, ANSI/ESD S20.20 draws no distinction between the ESD controls required for a "cheap throw-away" consumer electronics item versus an electronic item used for life support or other high reliability purposes. Here again, we may want to add additional controls or adjust limits.
EOS/ESD Association recently created a working group (WG-19) to address high reliability products and processing of sensitive items with withstand voltages below 100 volts HBM and 200 volts.
The purpose of this workshop is to introduce participants to the WG-19 efforts and to have an open discussion of some possible ways to modify ESD practices in order to address these two areas of concern.
This workshop will discuss recent advances to the ANSI/ESDA/JEDEC JS-001 HBM standard (such as Table 2A combinations and sampling advances) and ANSI/ESDA/JEDEC JS-002 CDM standard (such as the new test condition (TC)) methodology and hardware/metrology/calibration). Have a specific question or concern, or have experience with applying these tests to devices, or want to learn more? Please join us in what we expect to be a lively discussion on applications and future directions for both standards.
Workshop Session B: Wednesday September 13th
5:30 p.m. - 7:00 p.m. (Parallel Sessions)
B.1 EDA for Latch-up: Which are the Most Suitable Approaches?
Moderators: Michael Khazhinsky, Silicon Laboratories, Inc.; Krzysztof Domanski, Intel Deutschland GmbH
The verification of latch-up protection in modern integrated circuits is a difficult challenge. There are several factors including increasing design and process complexity, higher-pin counts, use of mixed voltages, power management, etc. that make latch-up analysis especially challenging.
EDA checking/verification tools to design for effective latch-up protection are getting used more and more. This includes traditional DRC tools for latch-up geometrical rule checking as well as voltage awareness and resistance analysis checking tools.
Come share what your experiences are in the field. Do you feel you have the right tools to identify the most important potential failures? Is accurate verification for preventing conventional internal latch-up your main concern? Are special cases like biased/floating wells, grounded n-wells, transient latch-up, high voltage applications more important for you? Is information for running the EDA tools readily available throughout design flow? What more is needed to reduce/eliminate latch-up design escapes/failures? Bring your experiences and thoughts/innovations.
New "World Café" Style Format!
ESD protection concepts and EMI sensitivity have a close interaction, as improving ESD robustness of the IO typically lowers the impedance of the IO circuit under interference conditions when for example diodes get forward biased. Also very aggressive ESD power clamps can fire at EMI related supply noise leading to a soft fail of the system. In extreme cases, EMI events will even cause latch-up. These design challenges provide enough motivation to select ESD/EMI codesign for an interactive EOS/ESD Symposium workshop, where experience and questions will be shared. Please join, learn, and contribute!
B.3 Machine Model and the Impact on Manufacturing
Moderators: Charles McClain, Micron Technology, Inc.
The goal of this workshop is to have a dialogue on the need to verify charged conductors and the potential effects on ESDS items in EPAs. Often referred to as machine model (MM) we will be discussing the differences between MM (from a device reliability standpoint) and what is seen on the factory floor when charged conductors influence ESD stability in all processes requiring ESD control. This could be in production or laboratory settings. This workshop is aimed at generating discussion between factory control and device test, why MM was removed from the design qualification requirements, and what that means inside the EPA.
Please bring your experiences and expertise to this exciting cooperative workshop.