Symposium Technical Presentations
TUESDAY, September 12, 2017
1A: Advanced CMOS I
10:20 a.m.-12:00 p.m.
Moderator: Robert Gauthier, GLOBALFOUNDRIES, Inc.
1A.1 DNW-Controllable Triggered Voltage of the Integrated Diode Triggered SCR (IDT-SCR) ESD Protection Device
Da-Wei Lai, Wei-Jhih Tseng, Gijs de Raad, Theo Smedes, NXP Semiconductors
A novel integrated diode triggered SCR (IDT-SCR), with low capacitance (<200 fF), and a controllable VT1 is proposed for 1.8 volt applications. The triggering is determined by the deep N-well (DNW) biasing plus one integrated diode. The fail-current density is 16 times higher, and leakage 20 times lower, compared to a traditional capacitive-triggered bigFET.
1A.2 Deep N-well Induced Latch-up Challenges in Bulk FinFET Technology
Chien-Yao Huang, Yu-Ti Su, Tzu-Heng Chang, Chia-Wei Hsu, Jam-Wem Lee, Kuo-Ji Chen, Ming-Hsiang Song, TSMC
Deep N-well (DNW) induced latch-up characteristics, and their temperature dependence, are investigated in bulk FinFET technology. DNW enclosed NMOS in PNPN and PNPNPN structures causes high latch-up susceptibility and low immunity against hot temperature. Varied methods are explored for holding voltage improvement. In summary, shunting resistance reduction through process design co-optimization plays a critical role in solving DNW induced latch-up challenges.
1A.3 Enhanced nFinFET ESD Performance
Jian-Hsing Lee, Manjunatha Prabhu, Natarajan Mahadeva Iyer, Edmund Banghart, Ronghua, Yu, Richard Poro, You Li, Shesh Mani Pandey, Robert Gauthier, GLOBALFOUNDRIES, Inc.
A very simple and useful scheme to enhance the ESD performance of nFinFET is reported. Incorporating the N-Well (NW) with the nFinFET, it becomes the low holding-voltage SCR if the NW contact is the ohmic-contact and becomes the high holding-voltage SCR if the NW contact is the Schottky contact.
1A.4 Oscillation of RC Power Clamp Inside IC Package RCJ Invited Paper
Tadashi Ozawa, Shin-Ichiro Ueno, Shingo Sasaki, MegaChips Corporation
One trigger could lead to continuous oscillation when it comes to some clamp types of RC with multiple-stage inverters. A principle solution for this is adopting one-stage inverter. Transient behaviors of clamps with multiple-stage inverters and one with one-stage inverter after triggering are discussed.
1B: Manufacturing I
10:20 a.m.-12:00 p.m.
Moderator: Wolfgang Stadler, Intel Deutschland GmbH
1B.1 EMI Generated EOS in a Wire-Bonder
Tim Iben, Michelle Lam, IBM; Vladimir Kraz, OnFILTER, Inc.
Wire-bonding equipment is essential to modern electronics manufacturing lines. Equipment, such as motors, either from components within or external to the wire-bonder, can generate EMI. This is a study of EMI on a wire-bonder, determining the EOS levels, the potential for damage to sensitive electronics devices, and means of eliminating the unwanted EMI.
1B.2 ESD Risk Assessment Considerations for Automated Handling Equipment
L.H. Koh, Y.H. Goh, W.F. Wong, Everfeed Technology Pte. Ltd.
ESD risk assessment considerations for two units of die attached and wire bonder machines were evaluated with reference to ANSI/ESD SP10.1. Modelling and simulation was proposed and discussed to evaluate the sensitivity of the automated handling equipment ESD performance.
1B.3 An ESD Case Study with High Speed Interface in Electronics Manufacturing and its Future Challenge
Rita Fung, Richard Wong, James Tsan, Jatin Batra, Cisco Systems, Inc.
A networking semiconductor component with 25 Gbps high speed interface experienced high manufacturing failure rate with CDM-like failure signature at contract manufacturer. Design experiment was performed and ESD source was located. Problem details, its future challenge, and required changes are discussed in this paper.
1B.4 Charged Device Discharge Measurement Methods in Electronics Manufacturing
Pasi Tamminen, Tampere University of Technology; Jeremy Smallwood, Electrostatics Solutions Ltd.; Wolfgang Stadler, Intel Mobile Communications
Electrical components with a lower CDM ESD immunity can require additional protection methods in manufacturing. Discharge current measurements and electromagnetic pulse detection give valuable data for more detailed ESD risk assessments. However, both methods require sophisticated tools and trained personnel to get accurate data for control purposes.
Hands On Session I NEW SESSIONS!
1:10 p.m. - 2:40 p.m.
Moderator: Dale Parkin, Seagate Technology; Wolfgang Stadler, Intel Deutschland GmbH
Measurement in ESD Control Standards
In this hands-on session you will have the opportunity to learn to know and understand the measurements defined in EOS/ESD Association, Inc. manufacturing standards, including the compliance verification measurements described in ANSI/ESD TR53. Learn from and discuss with leading experts, working group chairs, and members of EOS/ESD Association, Inc. standardization groups regarding current qualification, compliance verification techniques, and future trends.
2A: RF / High Voltage I
1:20 p.m. - 2:35 p.m.
Moderator: Ann Concannon, Texas Instruments, Inc.
2A.1 High Blocking Voltage ESD Timer Clamp with Mis-trigger Protection
Sirui Luo, Srivatsan Parthasarathy, Javier A. Salcedo, Jean-Jacques Hajjar, Analog Devices, Inc.
A supply clamp architecture is presented; which ensure a reliable low leakage performance at the higher supply voltage. An active feedback network designed into the supply clamp architecture ensures uniform clamping through the duration of the ESD event. Mis-trigger immunity is additionally incorporated to ensure reliable functionality up to 5 volts.
2A.2 On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism
Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan, Mayank Shrivastava, Indian Institute of Science
This experimental study reports ESD behavior of novel designs of GaN Schottky diodes. Impact of electro-thermal transport, device degradation, and trap generation on its ESD robustness is analyzed. Role of interface traps in ESD failure of GaN Schottky diode is investigated. Transition from soft-to-hard failure, which was found to depend on diode area, presence of traps, and diode design is discussed. Unique degradation trends, cumulative nature of degradation, and trap assisted failure modes are discovered.
2A.3 Circuit under Pad Active Bipolar ESD Clamp for RF Applications
Dolphin Abessolo-Bidzo, Eric Thomas, NXP Semiconductors
With the rapidly increasing RF complexity of RF BiCMOS designs for key mobile and internet of things (IoT) applications, achieving both extreme RF performance and ESD reliability requirements has become a big challenge. In this paper, a novel active bipolar clamp is proposed featuring circuit under pad for RF applications.
2B: ESD Failure Case Studies I
1:20 p.m. - 2:35 p.m.
Moderator: Adrien Ille, Infineon Technologies
2B.1 Window Effects in HBM and TLP Testing
Theo Smedes, Wolfgang Scheucher, Dolphin Abessolo-Bidzo, NXP Semiconductors
Presentation is a study of products showing systematic window effects during HBM and TLP testing. It is shown that the window effects are mainly the consequence of race conditions between different ESD current paths. Window effects are sometimes difficult to detect, but are in principle relatively easy to prevent.
2B.2 On the ESD Behavior of Pentacene Channel Organic Thin Film Transistors
Rajat Sinha, N.K. Kranthi, Mayank Shrivastava, Sanjiv Sambandan, Indian Institute of Science
For the first time, detailed physical insight into the ESD behavior and unique failure mechanisms of pentacene organic thin film transistors (OTFTs) is reported. Orders of magnitude difference in channel current under ESD time scales, when compared to DC time scales, is discovered. Moreover, unique three stage TLP characteristics with snapback state and novel failure mechanism are reported. Finally, influence of channel field and surface assembled monolayer (SAM) on the carrier transport and failure threshold is addressed.
2B.3 ESD Protection Structure Enhancement Against Latch-up Issue using TCAD Simulation
Johan Bourgeat, Nicolas Guitard, Florence David, STMicroelectronics
An unexpected ESD structure triggering has been observed during latch-up IO qualification in CMOS 28 nm bulk technology. The test result gives a clear overview of the parasitical event and shows a strong interaction between two abutted IOs during negative injection mode. The understanding of the phenomenon is clearly identified using TCAD simulations. Furthermore, some key design improvements are also given to reach an efficient latch-up immunity.
3A: System Level ESD I
3:30 p.m. - 5:10 p.m.
Moderator: Harald Gossner, Intel
3A.1 Risk Assessment of Cable Discharge Events
Wolfgang Stadler, Josef Niemesheim, Andreas Stadler, Sebastian Koch, Harald Gossner, Intel Deutschland GmbH
A rigorous measurement set-up, parameter extraction procedure, and SPICE simulation approach are presented which allow assessing the risk of ESD events caused by plugging a charged cable to a port of an electronic system (cable discharge events). The feasibility of the approach has been demonstrated on various USB-3 cables.
3A.2 Charged Device ESD Threats with High Speed RF Interfaces
Pasi Tamminen, Tampere University of Technology; Rita Fung, Richard Wong, Cisco Systems, Inc.
High speed RF interfaces operating in tens of Gbit/s range have limited ESD immunity. These interfaces are accessible when electro-mechanics are assembled on a printed circuit board. Charged device ESD threads due to charged assemblies with less than 1 pF source capacitances are discussed in this paper.
3A.3 Characterizing ESD Stress Currents in Human Wearable Devices
Abhishek Patnaik, Runbing Hua, David Pommerenke, Missouri University of Science and Technology
Currents induced on an I/O of a human wearable device IC are predicted using a test IC as a wearable device capable of transient event detection and level sensing. ESD on this pseudo wearable device using the test IC is characterized for different test scenarios and compared to the prediction.
3A.4 Scenarios of ESD Discharges to USB Connectors
Shubhankar Marathe, Pengyu Wei, Sun Ze, Li Guan, David Pommerenke, Missouri University of Science and Technology
Different real world scenarios which may cause stress voltages on USB connected devices are investigated by capturing the ESD induced currents for different discharge situations. The goal of this study to identify ESD discharge scenarios and their respective currents levels, stress duration, and the rise time of the measured waveforms.
3B: EOS/ESD EDA Tools
3:30 p.m. - 5:10 p.m.
Moderator: Michael Khazhinsky, Silicon Laboratories, Inc.
3B.1 An Automated Tool for Minimizing Product Failures Due to Parasitic BJTs and SCRs
Radu Secareanu, Craig Johnson, Michael Stockinger, NXP Semiconductors
A comprehensive methodology to locate and report parasitic BJTs and SCRs that are at risk of turning on due to transient events is described. The intuitive, DRC-like implementation identifies parasitic devices classified per their risk level, offering the opportunity to fix potential design issues during the design cycle.
3B.2 EDA Checker for Identification of Excessive ESD Voltage Drop – Implementation to Smart Power IC’s
Eleonora Gevinti, Gabriele Salzone, Lorenzo Cerati, Antonio Bogani, Stefano Angeli, Antonio Andreini, Leonardo Di Biccari, Luca Merlo, STMicroelectronics
A customized checker able to calculate HBM voltage drop and to identify product circuitry prone to excessive overvoltages is ideated, implemented, and successfully applied to smart power products. This checker is conceived as part of a complete verification flow covering all main aspects of IC designs ESD compliance.
3B.3 HV Latch-up - Power Analog ICs Co-Design with Block Level Verification
Todd Mitchell, Vladislav Vashchenko, Maxim Integrated; Terry Meeks, Mentor Graphics
A schematic and layout block level verification strategy based on verification automation is realized and applied for HV latch-up in power analog ICs design. The reasoning behind and some peculiarities of the methodology are presented as a co-design between schematic, layout, and latch-up specific parameterized cells.
3B.4 Influence of Self-Heating on ESD Current Distribution in Metal Lines
David Alvarez, Nitesh J. Trivedi, Michael Asam, Infineon Technologies
Copper metal lines from a 40 nm CMOS technology are investigated by means of TLP, electro-thermal simulations, and a current-density-check tool. The role of self-heating during ESD in the current re-distribution across metal paths of different resistance is demonstrated. Conclusions are drawn for the proper interpretation of EDA electrical current-density-check results.
Invited Speaker Session NEW SESSIONS!
3:40 p.m. - 5:00 p.m.
I: Beyond S20.20: Explosives
Jay Skolnik, Skolnik Technical Training
Discussion about the world of ESD mixed with explosives and energetic materials. Find out how manufacturing facilities are accommodating the needs of ESD control which differ from the electronics manufacturing arena. Case studies will be discussed, in addition to human safety versus product reliability.
II: IoT Challenges for Manufacturing
Michelle Lam, IBM; Terry Welsher, Dangelmayer Associates, LLC
The internet of things (IoT) brings big data analytics, artificial intelligence, process, and everything networked together to gain business value and insight. In this talk, let’s imagine what ESD control of the future could look like as IoT technologies start to transcend and transform the electronic industrial landscape.
WEDNESDAY, September 13, 2017
4B: Manufacturing II
9:20 a.m. - 11:10 a.m.
Moderator: Michelle Lam, IBM
4B.1 Qualification Challenges of Footwear and Flooring Systems
Toni Viheriäkoski, Cascade Metrology; Vesa Jokinen, Sievin Jalkine Oy; Jeremy Smallwood, Electrostatic Solutions Ltd.; Ari Korpipää, Armeka Engineering; Pasi Tamminen, Tampere University of Technology
Body voltage measurement may result in erroneous conclusions in the qualification of footwear and flooring systems in combination with a person. Measurement uncertainties shall be taken into account. We have studied a time dependency and a charge generation of footwear and flooring systems. The most significant inconsistencies of the voltage measurement are discussed in this technical paper.
4B.2 The Main Parameters Affecting Charged Device Discharge Waveforms in CDM Qualification and Manufacturing
Pasi Tamminen, Tampere University of Technology; Jeremy Smallwood, Electrostatics Solutions, Ltd.; Wolfgang Stadler, Intel Mobile Communications
Charged device model (CDM) discharges in a CDM qualification and charged device discharges in electronics manufacturing, are compared to evaluate the main discharge parameters. Accurate charged device ESD risk assessments would require the use of discharge current waveform information and tailored measurement methods.
4B.3 Electrostatic Discharge Characteristics of Conductive Polymers
Toni Viheriäkoski, Cascade Metrology; Eira Kärjä, Premix Oy; Reinhold Gärtner, Infineon Technologies; Pasi Tamminen, Tampere University of Technology
ESD control items are generally characterized by direct current measurements at certain voltage levels. Discharge resistance may, however, have a remarkable voltage and frequency dependency. We have assessed conductive polymers by comparing the resistivities of the solid planar objects with the resistances of electrostatic discharges. Conductive polymers may have applicable characteristics of current attenuation for ESD control items.
4B.4 Measuring the Body Voltage on Wearers of Category 3 Bunnysuits
Lawrence Levit, LBL Scientific; Christopher Lemke, Trek, Inc.; Michael Rataj, Aramark, Inc.; Geoffrey Weil, Anodyne Research
The electric field sensitivity of modern photolithographic reticles requires a category 3 bunnysuit with a body voltage limited to 100 volts. A charge plate monitor (CPM) is specified to measure body voltage. This paper investigates the measurement accuracy. It is shown that the capacitance of measurement system causes the CPM to underestimate the walking voltage.
4B.5 Charged Insulators: Tapes and Labels
Tom Rogers, Polyonics
A method for measuring the electric field generated from tapes and labels during simulated assembly operations is presented. Tapes and labels using polyester and polyimide materials used in PCB assembly can charge to very high levels. In comparison, voltages of similar tapes and labels using static dissipative coatings show significantly lower voltages.
4B.6 ES Defensive Resistance
Ed Cavaliere, L3 Technologies
This poster describes defense strategies against ESD discharges in manufacturing. Preventing materials from charging or providing proper resistance in all part contact points reduces discharge currents below the damaging level. Focus on knowing your part’s susceptibility by scouting and planning, then implementing the proper defense.
4A: On-Chip Physics
9:40 a.m. - 11:20 a.m.
Moderator: Mayank Shrivastava, Indian Institute of Science
4A.1 Transient Electromagnetic Co-Simulation of Electrostatic Air Discharge
Darwin Li, Jianchi Zhou, Ahmad Hosseinbeig, David Pommerenke, Missouri University of Science and Technology
Transient electromagnetic co-simulation is used to simulate the currents in a discharging rod. The simulation model simultaneously solves Maxwell’s equation and the arc resistance equations in time domain to estimate the currents and fields for a given geometry, charge voltage, and arc length. The Rompe-Weizel model is used to obtain the time dependent arc resistance, and results from different simulation methods are compared to measured data.
4A.2 FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection
Milova Paul, B. Sampath Kumar, Mayank Shrivastava, Indian Institute of Science; Christian Russ, Harald Gossner, Intel Deutschland GmbH
For the first time, physical insights into the missing SCR action in planar equivalent Fin SCR devices are presented; which has leveraged exploring challenges and fundamental roadblock in designing Fin SCRs. Key role of contact silicidation in Fin technology is discovered. The new understanding has allowed engineering conventional designs to resume SCR action. Finally, a novel Fin SCR design is disclosed, which offers an area efficient current conduction beside device scalability.
4A.3 How to Build a Generic Model of Complete ICs for System ESD and Electrical Stress Simulation?
Michael Ammer, Infineon Technologies, Universitat der Brundeswehr Munchen; Friedrich zur Nieden, Andreas Rupp, Yinqun Cao, Infineon Technologies; Martin Sauter, Linus Maurer, Universitat der Brundeswehr Munchen
For precise system ESD simulation, the transient chip behavior needs to be modeled accurately. As there are several typical characteristics possible, a straight forward methodology to build a generic model for transient behavior with destruction limits in SPICE is presented. This enables full-system transient ESD simulation for system robustness evaluation.
4A.4 Empirical ESD Models for Cascade ESD Transistors
Efraim Aharoni, TOWERJAZZ, Kinneret College on the Sea of Galilee; Avi Parvin, Yosi Vaserman, Alfred Yankelevich, Aharon Unikovski, Israel Rotstein, Raz Reshef, TOWERJAZZ
This work describes the development of empirical simulation models for cascade ESD transistors. Behavioral language VerilogA code was used to combine regular SPICE modeling with TLP characteristics at triggering voltage dependent on two gate voltages. The empirical models use for quantitative optimization of ESD protection circuits is demonstrated on schemes.
Hands On Session II NEW SESSIONS!
1:05 p.m. - 3:05 p.m.
II.A How to Detect ESD Events by EMI (ESD Event Detectors, Antenna, and Scope)?
Details coming soon!
II.B Detecting and Solving EMI Problems in Manufacturing
Moderator: Vladimir Kraz, OnFILTER, Inc.
EMI is omnipresent in a manufacturing environment. To reduce its negative effects on process, equipment, and devices, proper measurement methodology and effective mitigation methods must be employed. This short demonstration will illustrate the complete process of generating EMI on AC power lines and ground, its measurements, and its successful mitigation.
II.C Measuring Grounds in a Facility
Moderator: Jay Skolnik, Skolnik Technical Training
Learn about the proper techniques for ground impedance measurements in a facility. Find out the reasons some ground measurements fail to yield correct results and how to overcome these obstacles. Learn about DC resistance versus AC impedance, pitfalls with standard dmm’s, ground loops, phantom voltages, and more.
II.D ESD Field Measurement Pitfalls and ESD Voltage Suppression Demonstration (ANSI/ESD S20.20 and IEC61340-5-1 Differences)
Moderator: Ted Dangelmayer, Dangelmayer Associates, LLC
Evolving ionization technology provides new ionizer designs for static control, and test methods for these devices are needed. This session describes performance tests for air assist bar ionizers, soft X-ray (photon) ionizers, and an alternate method of room ionization. These test methods are proposed to augment existing industry standards.
5A: Testing I
1:35 p.m. - 2:50 p.m.
Moderator: David Eppes, Advanced Micro Devices
5A.1 Wafer Level Test Methodology for HV Latch-up Spacing Rules Development in BCD Process Technologies
David Marreiro, Vladislav Vashchenko, Maxim Integrated Corp.
A wafer-level latch-up test methodology was developed to address latch-up structure complexity and diversity in HV BCD process toward the development for HV latch-up spacing rules. The proposed approach is validated by multi-point comparison of the component level experimental results with JEDEC-compliant standard industrial tester and against process technology variations.
5A.2 An ESD Demonstrator System for Evaluating the ESD Risks of Wearable Devices
Jianchi Zhou, Zach Legenzoff, Xin Yan, David Pommerenke, Missouri University of Science and Technology; John Lee, Samsung
An ESD demonstrator system was designed to demonstrate the levels of transient fields and currents that a wearable device can be subjected to. The system can detect pulses as short as 1-2 ns and was used to evaluate the fields associated with a waist mounted discharge of a wearable device.
5A.3 Correlation Study of Different CDM Testers and CC-TLP
Johannes Weber, Horst Gieser, Heinrich Wolf, Linus Maurer, Fraunhofer EMFT; Karim T. Kaschani, Nicolai Famulok, Reinhardt Moser, Krishna Rajagopal, Michael Sellmayer, Anmol Sharma, Heiko Tamm, Texas Instruments
The paper compares the reproducibility of CDM test results of three different tester types with corresponding results of contact-mode capacitively coupled transmission line pulsing (CC-TLP). We further demonstrate first results of a simulation study about the correlation between CDM and CC-TLP.
5B: RF / High Voltage II
1:35 p.m. - 2:50 p.m.
Moderator: Mototsugu Okushima, Renesas Electronics
5B.1 Schottky LDNMOS for HV ESD Protection
Jian-Hsing Lee, Natarajan Mahadeva Iyer, Ruchil Jain, Tsung-Che Tsai, GLOBALFOUNDRIES, Inc.
A very simple and useful scheme to improve the ESD performance of HV LDNMOS is reported. Removing the N+ implant from the drain, the silicide to NDDD junction of HV LDNMOS becomes a Schottky junction. This modification can incorporate a Schottky pnp into LDNMOS to make it become the SCR.
5B.2 High-Performance Bi-Directional SCR Developed on a 0.13 um SOI-based Smart Power Technology for Automotive Applications
Carol Rouying Zhan, Patrice Besse, Jean-Philippe Laine, Alain Salles, NXP Semiconductors
Novel bi-directional SCRs have been developed on an advanced 0.13 um SOI-based smart power technology. Leveraging the benefits of the SOI, the SCRs achieved high and adjustable Vh with new NBL/collector and base engineering techniques. Outstanding DC, TLP, IEC61000-4-2, and EMC performance were achieved for automotive applications.
5B.3 Low Capacitive Dual Bipolar ESD Protection
Ilse Backers, Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal, Bart Keppens, Sofics BVBA
This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces up to 50%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.
6A: System level ESD II
3:20 p.m. - 5:00 p.m.
Moderator: Benjamin Orr, Intel Corporation
6A.1 Chip-Level ESD-Induced Noise on Internally and Externally Regulated Power Supplies
Yang Xiu, Nicholas Thomson, Robert Mertens*, Collin Reiman, and Elyse Rosenbaum, University of Illinois at Urbana-Champaign; *Now with NXP Semiconductor
Power integrity during system-level ESD is studied on two test chips that have different integrated voltage regulator designs. On-chip voltage regulation can provide increased immunity to ESD-induced noise, especially if the internally-generated power supply does not utilize any off-chip decoupling capacitors.
6A.2 On-Chip Monitors of Supply-Noise Generated by System-Level ESD
Nicholas Thomson, Collin Reiman, Yang Xiu, Elyse Rosenbaum, University of Illinois at Urbana-Champaign
On-chip supply noise monitors are introduced and used to sense the effects of system-level ESD at the IC level.
6A.3 Secondary ESD Event Monitoring and Full-Wave Modeling Methodology
Shubhankar Marathe, Darwin Li, Hossein Rezaei, Pengyu Wei, Jianchi Zhou, Ahmad Hosseinbeig, David Pommerenke, Missouri University of Science and Technology
An adjustable spark gap structure is designed to generate secondary ESD, measured directly using the current target. The setup is modelled using CST full-wave simulation software. The goal is to predict secondary ESD induced current levels using simulation methods, to assist designers in product development in the early design stage.
6A.4 Industrial and Automotive ESD, EFT, and Surge Generator Models to Predict EMC Robustness on ICs and Systems
Claire Leveugle, Thorsten Weyl, Analog Devices, Inc.
This paper presents a novel methodology to develop and validate disturbance generator models for a virtual EMC lab. New simulation models for ESD, EFT, and surge stimuli have been created and verified on a wide range of load conditions.
6B: Advanced CMOS II
3:20 p.m. - 4:35 p.m.
Moderator: Theo Smedes, NXP Semiconductors
6B.1 VFTLP Characteristics of ESD Diodes in Bulk Si Gate-all-Around Vertically Stacked Horizontal Nanowire Technology
Shih-Hung Chen, Geert Hellings, Mirko Scholz, Dimitri Linten, Hans Mertens, Romain Ritzenthaler, Anda Mocuta, Naoto Horiguchi, imec; Roman Boschke, Guido Groeseneken, KUL Leuven
For sub-7 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have impact on the transient performance of an ESD protection diode. VFTLP measurement results and TCAD simulations prove that the performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.
6B.2 Novel SCR Structure for Power Supply Protection in FinFET Technology
Po-Lin Peng, Li-Wei Chu, Yi-Feng Chang, Wun-Jie Lin, Chia-Wei Hsu, Kuo-Ji Chen, Ming-Hsiang Song, Jam-Wem Lee, Taiwan Semiconductor Manufacturing Company
A FinFET SCR embedded ESD clamp for power supply protection with low leakage current is demonstrated. The proposed clamp is suitable for low power applications since it reduces ~87% of leakage current per bigFET width and improves ESD robustness to ~2X per footprint, compared to the conventional RC-triggered clamp.
6B.3 A Novel, SCR-Based, Distributed Power Supply ESD Network for Advanced CMOS Technologies
Gianluca Boselli, Muhammad Yusuf Ali, Texas Instruments, Inc.
In this work, a novel, dual-diode ESD cell with embedded lateral SCR between power supplies is presented (DDESCR). The triggering voltage of the DDESCR is remotely modulated through the triggering circuit of the power supply ESD cell. A highly area-efficient distributed SCR ESD network is demonstrated.
Tutorial Session I NEW SHORT TUTORIAL SESSIONS!
3:25 p.m. - 5:10 p.m.
I.A Cable Discharge Events in Assembly and Testing
Reinhold Gaertner, Infineon Technologies
More and more people report about discharge from or via cables that can damage devices or systems that are quite robust against ESD gun pulses. In these cases ESD might occur as a discharge of a cable which is known as cable discharge event (CDE) or as a discharge of a device or a human being via a cable into an interface. Typical discharge waveforms show a sharp initial current peak, followed by a transmission line pulsing (TLP) like plateau which is caused by the discharge of the cable itself. In this tutorial typical examples from the field are shown as well as typical waveforms of cable discharges and how they can be measured.
I.B Packages, Tape & Reel, Trays, and Others: How to Assess ESD Compliance?
David E. Swenson, Affinity Static Control Consulting, LLC
Some forms of packaging do not lend themselves to normal measurements normally used for bags, films, wraps, boxes and other planar materials. Tape & Reel and trays often have very fine and small features that do not allow for accurate placement of measurement electrodes. The IEC committee for Electrostatics - TC101, has a joint working group with TC40 - Capacitors and Resistors to look into testing of the small feature packaging materials. This short Tutorial will give a quick overview of some of the measurements that are possible for evaluation of these packaging forms.
I.C New Methods if Air Ionizer Performance Testing
Arnold Steinman, Electronics Workshop
The ionization standard test method, ANSI/ESD STM 3.1, defines procedures and instrumentation for measuring discharge time and offset voltage for several types of air ionizers. Additional test methods for the same ionizers are contained in both ANSI/ESD SP3.3, Periodic Verification of Air Ionizer Performance, and ESD TR53, Compliance Verification of ESD Protective Equipment and Materials. However, measurement methods are needed for newer ionizer designs not covered by existing ionization test methods.
This tutorial discusses test procedures for other types of ionizers, including air-assist bar ionizers, soft x-ray ionizers, an alternative method of room ionization, and non-airflow alpha ionizers. Discharge time and offset voltage testing is proposed, using the same measurement equipment as in ANSI/ESD STM 3.1, but at new test locations and measurement distances. The procedures will address test conditions such as compressed air pressures, air volume, interlock systems and laminar flow. The material discussed in this tutorial will soon be published in a new EOS/ESD Association, Inc. standard practice SP3.5.
THURSDAY, September 14, 2017
7A: ESD Failure Case Studies II
8:50 a.m. - 10:05 a.m.
Moderator: Tim Iben, IBM
7A.1 Cross-Domain Interaction at System Level Stress
Vladislav Vashchenko, Dimitrios Kontos, Maxim Integrated; Andrei Shibkov, Angstrom Design Automation
A scenario of failures of unrelated LV analog domains at system level stress has been studied both experimentally using test structures and through mixed-mode numerical simulation. The analysis of the failure mechanism and validated design fix measures are presented.
7A.2 Analysis and Solution to the ESD Failure Caused by Plasma Protection Diodes for MIM Capacitors
Jian Liu, Nate Peachey, Qorvo, Inc.
This paper introduces the analysis of an ESD failure caused by plasma protection diodes for MIM capacitors in an SOI CMOS technology. TLP ESD testing and transient ESD simulations were employed to identify the reason for the failure, confirmed by OBIRCH. Solution was proposed and verified by simulation and measurement.
7A.3 Effective HBM Protection to Prevent Voltage Overshooting of Gate-Coupled SCR
Zhong Chen, University of Arkansas; Gianluca Boselli, Texas Instruments, Inc.
Case study on HBM ESD protection using gate-coupled SCR is presented. The failure mechanism of DENMOS devices due to the voltage overshooting of SCR is discussed. It is demonstrated that effective HBM protection cannot be estimated by only comparing the TLP triggering voltage of gate-coupled SCR and internal circuitry. Additional protection scheme need to be implemented to provide sufficient HBM ESD protection.
Discussion Group Session NEW SESSIONS!
8:50 a.m. - 10:20 a.m.
DG.A CDM Manufacturing Controls for Class 0 (0B & 0A)
Moderator: Ted Dangelmayer, Dangelmayer Associates, LLC
The objective of this group discussion is to clarify confusion regarding CDM control methods for Class 0 ESD sensitive devices. The benefits of current discharge measurements, surface resistance, dissipative materials and avoidance of metal-to-metal contact will be explored. The limitations of industry standards will be discussed as well as the CDM considerations in the various standards.
DG.B Electrical Overstress in Manufacturing – Mitigation Strategies and Standards
Moderators: Scott Ward, Texas Instruments, Inc.; Terry Welsher, Dangelmayer Associates, LLC
While attention to the root causes of electrical overstress (EOS) damage has increased in recent years, most of the focus has been on failures that occur in the field as opposed to device and board manufacturing and test. This discussion group will center on participants experience with EOS damage in manufacturing and actions they have taken to prevent future yield losses. The possibility of a comprehensive EOS Control Program will also be discussed.
DG.C ESD Control Program Management for Contract Manufacturing
Moderator: Charles McClain, Micron Technology, Inc.
Your company has an effective and efficient company-wide ESD control program. How do you, as the ESD coordinator, ensure that your contract manufacturing partners adhere to the same ESD control requirements? Challenges arise when critical technical differences exist between the two programs. These differences are even more dramatic if your contract manufacturer’s program was customized to meet the needs of another company’s requirements and are out of alignment with your requirements.
ANSI/ESD S20.20 facility certification is a possible solution, provided both adhere to the ANSI/ESD S20.20 program. If ANSI/ESD S20.20 requirements are not adhered to, what are the potential pit falls to watch out for? This is an important topic in a critical link between companies. Come discuss this amongst others in your same predicament, take back new ideas and provide insight and experience to the group.
8A: Testing II
10:25 a.m. - 11:40 a.m.
Moderator: Mike Chaine, Micron Technology, Inc.
8A.1 On-Chip Sensors to Measure Level of Transient Events
A. Patnaik, M. Suchak, R. Seva, K. Pamidimukkala, D. Beetner, Missouri University of Science and Technology; R. Moseley,J. Feddeler, M. Stockinger, NXP Semiconductors
On-die circuits were developed to measure the size of transient electrical events experienced at I/O pads. The circuits allow an IC to determine the peak voltages across the electrostatic discharge diodes during the event. Experiments and simulations with a 90 nm test chip show the promise of the approach.
8A.2 Proper Human Body Model Testing of High Voltage and "No Connect" Pins
Evan Grund, Grund Technical Solutions, Inc.
"No connect" pins were exempted from HBM testing due to tester delivery path parasitics producing an unintended CDM-like overstress. A modified two-pin HBM tester has been built that reduces overstressing to a level were valid testing of no connect pins and high voltage pins with snapback protection is possible.
8A.3 Correlation Limits between Capacitively Coupled Transmission Line Pulsing (CC-TLP) and CDM for a Large Chip-on-Flex Assembly
Johannes Weber, Horst Gieser, Heinrich Wolf, Linus Maurer, Fraunhofer EMFT; Wolfgang Reinprecht, ams AG
The study investigates expected limits of the correlation with respect to peak current and energy between contact-mode capacitively coupled transmission line pulsing (CC-TLP) and CDM for a sensitive chip-on-flex (COF) with long interconnect traces on polyimide film and the die at wafer level by means of experiment and simulation. The static potential distribution is measured.
Tutorial Session II NEW SHORT TUTORIAL SESSIONS!
10:40 a.m. - 12:25 p.m.
II.A Introduction to Shielding Bag Test – ANSI/ESD STM11.31
Dale Parkin, Seagate Technology; Ron Gibson, Advanced Static Control Consulting
Packaging plays a very important role in the development of a complete ESD control program. This tutorial will cover an introduction to ESD shielding bags and the shielding bag test – ANSI/ESD STM11.31. We will provide an overview of shielding bag construction (metal-in and metal-out) and we will describe the STM11.31 test and show how the test is performed. Finally, we will cover what does the waveform tells you about the bag and it’s construction.
II.B Charged Board Event and the Correlation to Charged Device Model
Pasi Tamminen, EDR&Medeso
Charged board event (CBE) is one of the main ESD scenarios found in electronics assembly environments. In the CBE, printed circuit boards and other electromechanical parts have static charges, and create stress on the components or ICs mounted on the board when the board or system is grounded. In this tutorial the CBE phenomena and CBE control methods are presented in detail. The tutorial includes CBE failure cases, measurement and simulation methods, and discusses how to use measured discharge parameters to evaluate system level CBE risk in electronics handling.
II.C "Meet the Standard" with History, Background, and Contents
Matt Strickland, L3 Technologies, Inc.; Ted Dangelmayer, Dangelmayer Associates LLC
EOS/ESD Association, Inc. has over 75 published documents that cover a range of subjects with regard to ESD control. It can become overwhelming to those new to the ESD control world to determine how to apply certain documents in what situations.This tutorial is designed to be a forum to provide those responsible to implement ESD Control programs an overview of a few important standards and how to apply them in the factory.This tutorial will discuss the background, purpose, usefulness and limitations of four of the many standards available from EOS/ESD Association, Inc.:
• ESD TR53-01-15 Compliance Verification Procedures
• ANSI/ESD STM11.11-2015 Surface Resistance
Measurements of Static Dissipative Planar Materials