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2017 Symposium Program pdf

ANSI/ESD S20.20 Seminar

Sunday and Monday, September 11-12

FC340: ESD Program Development and Assessment
(ANSI/ESD S20.20 Seminar)
8:00 a.m. - 5:00 p.m.
David E. Swenson, Affinity Static Control Consulting, LLC; Kevin Duncan, Seagate Technology

Certification: PrM

The ANSI/ESD S20.20 Seminar is intended to bring all the aspects of the program manager curriculum to a final focal point. The concepts of electrostatic control are discussed within the context of designing, implementing, and maintaining an effective ESD control program plan that meets the requirements of the standard.  Preparing a documented ESD control program plan that can withstand a 3rd party ISO9000 certification body is a major element of the certification process. Students are required to participate in numerous activities in this seminar to help acquaint them with the concepts involved in designing an ESD control program plan.

The following topics are covered in this course:

  • Overview of ANSI/ESD S20.20
  • How to approach an assessment
  • Administrative elements
  • ESD program assessment
  • ESD program techniques for different applications
  • Technical elements
  • Overview of the assessment process
  • The audit checklist and follow-up questions



FC100: ESD Basics for the Program Manager

8:30 a.m. - 4:30 p.m.
Stephen Halperin, Stephen Halperin & Associates, Ltd.

Certification: PrM

This presentation is a comprehensive introduction to the fundamentals of ESD causes and control. ESD Basics is a full-day seminar consisting of three presentation sections.

Part 1 includes an overview of ESD impact on industry, with detailed explanations of charge generation, field measurement, the role of capacitance and voltage, charge measurement, and charge decay.

Part 2 focuses on general explanations and illustrations of device failure mechanisms, including human body model, charge device and field induction models, and explains the machine model.

Part 3 is concerned with protecting ESD sensitive devices and assemblies, defining the electrostatic protected area (EPA), understanding various ESD control elements and material selection, and includes a brief introduction to ANSI/ESD S20.20 ESD program development criteria. Several demonstrations and opportunities for discussion make this an interesting introduction to ESD causes and control. No previous ESD experience necessary.

Sunday, September 10

DD110: ESD Basics to Advanced Protection Design

8:00 a.m. - 12:00 p.m.
Charvaka Duvvury, ESD Consulting, LLC

Certification: DD

This course gives a comprehensive overview from ESD basics to ESD on-chip design principles, covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality. The attendee will have an in-depth understanding of the principles of ESD device design along with a full perception of what it takes to address almost every kind of design scenario, how to apply rules of thumb for successful on-chip design, knowledge of lessons learned from case studies, and empowerment to communicate with customers on ESD quality issues. In its complete ESD overview, the course offers emphasis on on-chip protection methods including an understanding of any interactions to the eventual system protection.

DD200: Charged Device Model Phenomena, Design, and Modeling

8:30 a.m. - 12:00 p.m.
Michael Chaine, Micron Technology, Inc.; Melanie Etherton, NXP Semiconductors

Certification: DD

This course teaches basic ESD circuit design concepts and ideas required to design ESD protection for charge device model (CDM) ESD tests. The course covers a brief history of CDM ESD development, charge and discharge physics, characterization methods, CDM failures mechanisms, and CDM design-in strategies.

CDM ESD circuit design approaches and simulation setups for CDM failure debugging are presented in this tutorial on the basis of case studies. Insight into CDM circuit simulation requirements and physical aspects of the CDM ESD phenomenon that are important for reproducing the event with circuit simulation will be taught, and modeling approaches for CDM specific device physical effects necessary for accurate circuit simulation will be introduced. This course also teaches methods for simplified CDM circuit simulations where detailed information is either not available or too complex to simulate.

The course focuses on what type of circuits fail during a CDM discharge event and teaches the different types of ESD design circuit strategies that can be applied to protect those circuits. This class covers basic to advanced topics for CDM ESD design, but the student is assumed to already have a basic understanding of the CDM test method.

DD/FC130: System Level ESD/EMI: Testing to IEC & Other Standards

8:30 a.m. - 12:00 p.m.
Jeff Dunnihoo, Pragma Design, Inc.

Certification: PrM, DD

This tutorial is intended to help those tasked with testing products to system level ESD standards by providing first an overview of how real-world system ESD events are simulated in different standards and testers in general, and then provide detailed information on IEC 61000-4-2, the most widely used standard. This introduction will highlight the similarities and differences between IEC, ANSI, Telcordia, and some automotive ESD standards. We will answer common questions regarding test setups, test points, and procedures, and address key issues, including: 1) differences between "verification" and "calibration" and when is each required; 2) test equipment requirements, the test environment, ground connections, return paths, and ground plane effects. 3) Testing procedures with demonstration on actual products, how the tester and procedure affects test results, and problems with test result variations due to simulator influences; 4) definitions of testing failure criteria for the product; 4) what points need to be tested and why, guidance on determining "operator accessible" points and ports, exempted points and ports, and what to do around connectors and connector pins. 5) ANSI and other ESD standards, the drive toward harmonization with IEC, the scope of different standards, and why they are unlikely to converge. This system level ESD tutorial will cover different perspectives on ESD as applied to electronic systems from the user’s, the designer’s, and even the designer’s competitor’s points of view.

DD/FC155: ESD Control Workstations: Set-up, Practical Considerations, and Measurements

8:30 a.m. - 12:00 p.m.
Ginger Hansel, Dangelmayer Associates, LLC

The complexity of properly installing workstations is often underestimated. On the ‘surface’ it appears to be a simple installation of an ESD static dissipative mat or ESD hard laminate. However, there are important issues learned from years of experience that impact cost, durability, ESD performance, maintenance, and compliance verification. A good ESD control workstation is the cornerstone of ESD program management (EPM). Workstations used in processing ESD susceptible items are intended to maintain a near zero potential by providing ground paths for basic components of the workstation and a connection point for personnel grounding apparatus. The workstation should provide protection from charged device model (CDM) ESD as well as human body model (HBM). This practical tutorial will teach you how to set-up an effective ESD controlled workstation that accomplishes these goals. It will cover selection and qualification of the required materials and how to install them correctly. Other workstation issues will be discussed including: application of ionization, garment grounding, ESD chairs, handling containers, tools, and compliance verification consistent with ESD TR53.

DD/FC161: Perfect ESD Storm

8:30 a.m. - 10:00 a.m.
Ted Dangelmayer, Dangelmayer Associates, LLC

Learn how to prepare for the "Perfect ESD Storm" that is brewing in the electronics industry. The trend towards extensive use of ultra-sensitive components (Class 0) and the widespread lack of charged device model (CDM) understanding are brewing the "Perfect ESD Storm." It is no longer business as usual, and it can take up to two years to prepare. This tutorial is intended for professionals who have a basic understanding of ESD but are not fully aware of CDM control techniques or the industry trend toward extremely sensitive devices and the counter measures that are necessary. Learn the answers to your questions as well as these examples: Are you skeptical about this news of a Class 0 trend? Is it really happening? Is it likely to be a problem in your factory? How big a problem is CDM in manufacturing? What is different about CDM controls? How do I tailor ANSI/ESD S20.20 for CDM and Class 0? Join us for this highly interactive tutorial and learn why this is inevitable and how to prepare for it.

NEWDD/FC330: Control of Charged Board Event (CBE)

10:30 a.m. - 12:00 p.m.
Pasi Tamminen, Tampere University of Technology

Charged board event (CBE) is an ESD phenomenon where printed circuit boards and other electrical systems are charging up and create stress on the components or ICs mounted on the board when the board or system is grounded. In this tutorial the CBE phenomena and CBE control methods are presented in detail. The tutorial includes CBE failure cases, measurement and simulation methods, and discusses how to use measured discharge parameters to evaluate system level CBE risk in electronics handling. The tutorial provides methods to detect, measure, and mitigate CBE risks in electronics handling.

DD201: ESD Protection and I/O Design

1:00 p.m. - 4:30 p.m.
Michael Stockinger, NXP Semiconductors

This tutorial is intended to provide the attendees with the tools to take a device and circuit level understanding of ESD protection methods and implement them effectively in I/O designs for CMOS bulk technologies. Beginning with a review of common ESD protection strategies, this course will focus more directly on how to build ESD-robust I/O cells and how to integrate them on a full chip. The tutorial will cover various types of I/O pads including analog, RF, and digital pads. Different types of ESD protection strategies and their usage in I/O pad cells will be described, for example, rail clamp, self-contained, and SCR based protection schemes. This course will also discuss the decisions and challenges which ESD and I/O designers typically face when designing I/O pads. More complex ESD solutions will also be described such as stacked rail clamps, ghost rails, and protecting signals that can swing below ground or above the supply. Finally, this tutorial will touch on various supply schemes including multiple power domains and isolated grounding schemes. It will end with discussing pad ring construction aspects for both wire-bond and flip-chip packages.

DD204: ESD Design in HV Technologies

1:00 p.m. - 4:30 p.m.
Lorenzo Cerati, STMicroelectronics; Yiqun Cao, Infineon Technologies

This tutorial gives an introduction to ESD design in high voltage technologies for integrated circuits with pin voltages from 12 volts upwards. After a short introduction of typical applications and requirements, an overview of different technologies and the typical device portfolios in these technologies will be given. Different ESD protection concepts are introduced, analyzing advantages and disadvantages of the various possible approaches to implement ESD networks (diodes, snapback devices, active clamps, etc.). Finally, HV technology and design related challenges regarding ESD protection are discussed, with a special focus on the formation of parasitic bipolar devices and the impact on the circuit’s ESD performance. The attendee will gain a good basic knowledge of the main characteristics of HV technologies, the different ESD protection concepts, and ESD protection challenges that are specific for HV technologies. This will be a help for understanding and further development of HV ESD protection. An extensive literature list is provided for further study of various subjects regarding HV ESD.

FC164: Costly Controversial ESD Myths

1:00 p.m. - 4:30 p.m.
Ted Dangelmayer, Dangelmayer Associates, LLC

There are a number of common misunderstandings and controversies about electrostatic discharge (ESD) program management that can have significant impact on the implementation and maintenance of the ESD program.  These misunderstandings or "myths" result in unnecessary expenditures and/or result in a compromise of the program integrity. These myths and controversies, such as latency, are often cited by skeptics not wanting to adhere to certain standard ESD procedures. As a consequence, it is important to identify and dispel the myths as well as to understand the potential impact of latent failures.

This tutorial highlights 10 common myths and supporting success studies as well as a success study on latency. The myths and success studies presented here were chosen to provide real-world examples of how an ESD program can be strengthened by understanding the fallacy in each of the myths.  This understanding will result in more reliable products that are also more cost competitive. Although not a myth, latency is a significant reliability consideration that is surrounded with controversy. Some experts will argue that latency is virtually non-existent and others will claim that it is the dominant failure mode. Reality lies somewhere in between. The latency study cites irrefutable evidence of latent failures in alarming proportions that must be factored into ESD programs and product design.

NEWFC370: Basics of EMI and EOS in Manufacturing Environment and Their Mitigation

1:00 p.m. - 4:30 p.m.
Vladimir Kraz, OnFILTER

High-frequency noise, known as EMI - electromagnetic Interference - causes a number of problems in an industrial environment, as well as in other applications - medical, R&D, data centers, and alike. These problems are divided into two main categories: interference with normal operation of equipment and EMI-caused electrical overstress (EOS). EMI leads to erratic operation of equipment, errors in test and measurements, and can even pose a safety hazard. "EOS is the number one cause of damage to IC components" according to Intel. Most companies have ESD under control; however, EOS is seldom addressed. Failure analysis often misdiagnoses EOS-caused failures as caused by ESD. Factories today do not have adequate knowledge to deal with the critical to yield and quality EOS exposure. This half-day course familiarizes factory engineers, technicians, and managers with the phenomenon of EMI and EMI-caused EOS, its quantification, problem diagnostics, and mitigation basics.

Course Objectives:

  • Understanding of EMI phenomenon
  • Understanding of EOS and how it is caused by EMI
  • Practical skills in EMI measurements at the factory
  • Understanding of basics of EMI mitigation
  • Understanding of basics of EMI audit

Participants of this course will learn practical fundamentals of EMI, how to manage EMI and EOS in their factories, and will be able to implement the new knowledge in practice.

TUTORIALS: Monday, September 11

FC101: How To’s of In-Plant ESD Auditing and Evaluation Measurements

8:30 a.m. - 4:30 p.m.
Ted Dangelmayer, Ginger Hansel, Dangelmayer Associates, LLC

Certification: PrM

Compliance verification is one of the most important elements of ESD program management and there are many technical and administrative pitfalls that can be avoided. The attendee will learn not only how to make valid auditing measurements in accordance with ESD TR53 – Compliance Verification of ESD Protective Equipment and Materials, but also how to recognize and avoid common pitfalls. Common instruments will be explained as well as the invalid test results that can result when they are used incorrectly. Advanced auditing techniques will also be covered that enable Class 0 devices to be handled successfully. There are many ways to administer effective compliance verification programs. Two successful examples will be presented that were developed independently by different companies. Hidden administrative pitfalls that often result in poor compliance will also be discussed. This tutorial will be highly interactive with live demonstrations, in-plant photographs, and compelling video clips. Students will be encouraged to ask questions and to participate in the discussions

NEW/REVISEDDD231: ESD System Level: Physics, Testing, Debugging of Soft and Hard Failures

8:30 a.m. - 12:00 p.m.
David Pommerenke, University of Missouri-Rolla

The tutorial is an expanded version of the previous DD231 tutorial on system level ESD. The main difference is the addition of many experimental demonstrations, update of information, and in-depth discussion on problems of the IEC 61000-4-2 testing, with examples on how to perform this testing and obtain the best possible results and documentation. About half of the time will be spent on experimental demonstrations.

Topics will include:

  • ESD physics: charging and discharging.
  • System level ESD testing
  • System level soft failure mechanisms and debugging
  • Design for avoiding ESD problems


DD103: An Overview of Integrated Circuit ESD: The ESD Threat, Testing, Design Concepts, and Debugging

8:30 a.m. - 12:00 p.m.
Alan Righter, Analog Devices, Inc.

Many integrated circuit (IC) designers do not have a working knowledge of ESD. This tutorial presents aspects of ESD that are relevant to IC designers and will enable them to improve their ESD track record. This tutorial will also be useful for a wide range of specialists including layout designers, I/O designers, test engineers, failure analysis engineers, quality and reliability engineers, and architects as well as ESD design engineers just entering the field. The student will learn the fundamentals of ESD design, know the variables which affect ESD robustness, understand that ESD design needs to be addressed early in the design cycle, and be better able to interact with ESD design specialists, understand ESD testing, and interpret failure analysis data.

FC360: Electrical Overstress (EOS) in Manufacturing and Test

8:30 a.m. - 12:00 p.m.
Reinhold Gaertner, Infineon Technologies

Electrical overstress (EOS) is a major cause of device failure in manufacturing and in the field. Despite this, there is relatively little information on the sources of EOS and on prevention practices, particularly for the factory. In this tutorial, the fundamentals of device overstress are reviewed. Relationships among device EOS stressing models, such as the Wunsch-Bell curve, are discussed. The causes of EOS and EOS-like events in manufacturing are described and categorized by source and by stress-type. The difficulties in distinguishing between power-induced EOS and high current ESD events such as charged-board events (CBE) and cable discharge events (CDE) are discussed. Case histories, including failure analysis and root cause determination, are presented and the few relevant industry specifications are reviewed.

FC200: Packaging Principles for the Program Manager

8:30 a.m. - 12:00 p.m.
David E. Swenson, Affinity Static Control Consulting, LLC

Certification: PrM

Shipping electronic parts within a factory, to another factory, distributor, or to an end-user has always been an area of uncertainty within the manufacturing process.

To provide clear-cut information on what type of controlled packaging should be used in any situation, EOS/ESD Association, Inc. released a comprehensive revision of the obsolete industry standard EIA 541-1988. The newer document, ANSI/ESD S541, is the focus of this inclusive session. It provides information and guidance, as well as material specifications, to assist in the design and implementation of a packaging plan for use within an ANSI/ESD S20.20 based ESD control program. Current and newly released test method standards suitable for packaging material evaluation will be described. Course credit applies to the ESD program manager certification curriculum. Previous attendance at the " FC100: ESD Basics" and "FC101: How To’s" tutorials are highly recommended.

DD213: ESD, EOS, and Latch-up Failure Analysis for Designers

8:30 a.m. - 10:00 a.m.
Jim Vinson, Intersil Corporation

This tutorial will introduce the student to the field of failure analysis (FA) as it is performed on ESD, EOS, and latch-up failures. This tutorial is not trying to make the student into a failure analyst. This takes 3-5 years of mentoring to cultivate. The emphasis will be on understanding the diagnostic process and applying the correct set of tools to the failure with the ultimate goal of determining a corrective action to improve the product’s robustness to these stresses. Examples will range from discrete clamp debug to FA on a complex circuit. FA combines the skill set of a detective, designer, and device physicist to understand what has happened to cause failure.

DD300: Circuit-Level Modeling and Simulation of On-Chip Protection

10:30 a.m. - 12:00 p.m.
Elyse Rosenbaum, University of Illinois at Urbana-Champaign

Certification: DD

This tutorial addresses modeling and simulation of protection circuit elements and networks under ESD conditions. The high-current characteristics and transient responses of devices typically used in ESD protection circuits will be presented. The objective is to ascertain what behaviors have to be captured in models intended for circuit-level simulation of ESD. Specific examples of model implementations will be provided. Parameter extraction and model scalability will be addressed. Thermal modeling will be discussed, as will be the issue of modeling the off-state behavior of ESD protection devices. This tutorial assumes some familiarity with device physics. It is directed toward persons with an interest in the transistor-level physics of ESD in on-chip protection circuits and an interest in computer-aided design.

NEWDD340: Integrated ESD Device and Board Level Design 

1:00 p.m. - 4:30 p.m.
Harald Gossner, Intel Deutschland GmbH

The tutorial is a hands-on training course for performing a simulation based optimization of PCB ESD protection design and provides deep understanding of the relevant performance criteria both of TVS diodes and IO circuits. The presented method follows the system efficient ESD design (SEED) approach as recommended by the Industry Council on Target Levels and JEDEC.

The method allows the achievement of correct first time PCB builds and reduces the respin effort for boards and ICs. Based on a TLP characterization of SoC interface circuits and TVS diodes, simulation models for impedance and clamping behavior, as well as failure threshold, are extracted. These are used to assess design solutions by transient simulations. This is showcased by real world examples.

DD319: Physical Process, Device, and Circuit Simulation (TCAD) Methodologies in Application to Industrial ESD Research and Design

1:00 p.m. - 4:30 p.m.
Vladislav Vashchenko, Maxim Integrated

Over the last two decades numerical simulation with commercially available technology CAD (TCAD) tools has been widely applied across industry and research organizations to address ESD protection design challenges, ESD solutions development, test chip design and validation of the device, clamp circuits, and application circuit blocks as well as interpretation of the failure analysis results. Corresponding significant and diverse material has been accumulated in the literature and unpublished industry practices. At the same time the best practices and methodologies were not adequately summarized to bring them a broader audience in an easily accessible and practical, usable way. As a result, these are way underused today.

The purpose of this tutorial is provide a comprehensive structured review of the published ESD TCAD results and construct a step-by-step approach to successful methodology and best practices application. The presented material achieves this goal in several steps: (i) means of review and classification of the most relevant studies where the ESD problems have been addressed through TCAD simulation; (ii) derivation of a generic physical simulation workflow based upon either process simulation or parameterized device definition followed by device simulation and mixed-mode analysis in ESD time domain; (iii) outlining and classifying the major application physical ESD problems which can be addressed through 2D or 3D TCAD analysis. The presentation material is supported by numerous easy-to-understand simulation examples. With fabless and fab-light trends dominating in the semiconductor industry in recent years, one of the main focus points of this tutorial is overcoming the requirements of well calibrated process simulation flow for successful application of the TCAD methodologies. This is done by demonstrating the classes of problems and solutions that can be addressed in this environment. Another focal point of this tutorial is to demonstrate the mixed-mode simulation approach capability including device and circuit parameterization and automation.

This tutorial is not linked to any specific TCAD tool set and is equally useful to the users with experience using TCAD tools from any vendor or to the ESD engineers providing problem statement input for TCAD engineers. The material is presented using physical problem statements and solutions to illustrate the efficiency of methodology for ESD practitioners and device engineers. The material is presented hierarchically on the levels of ESD device physics, clamps, and product circuit sub blocks including study of possible latch-up scenarios.

FC215: Device Technology and Failure Analysis Overview

1:00 p.m. - 4:30 p.m.
Jim Vinson, Intersil Corporation

Certification: PrM

This tutorial is designed to give an overview of ESD protection technology and design, as well as an overview of the debug techniques used when a circuit fails to meet ESD performance requirements. The three major areas addressed are 1) a general overview of ESD; 2) circuit protection techniques; and 3) failure analysis. Failure analysis is the key to identifying and correcting weaknesses in ESD designs. The tutorial is NOT intended to turn the student into an ESD device or circuit designer nor a failure analyst. Rather, it is meant for program managers and other support personnel who are involved in the product development process to gain a better understanding of the language and challenges encountered supporting ESD robustness in new designs. After completing this tutorial, the student will be exposed to the key specifications governing ESD robustness and the common device architectures used to provide that robustness. The tutorial will include real world examples of protection designs and electrical characterization of those designs, as well as go through the tools and techniques used to debug a design.

DD/FC380: Electrostatic Calculations for the Program Manager and the ESD Engineer

1:00 p.m. - 4:30 p.m.
Terry Welsher, Dangelmayer Associates, LLC

Certification: PrM

This tutorial focuses on the basic calculations and techniques of use to the program manager and the ESD engineer. The content is at the introductory college pre-calculus and introductory college physics level set in the context of electrostatic discharge and its effects. It is suggested that the student gain some familiarity with these subjects prior to the tutorial. Topics covered include the electric force, the electric field and Coulombs law, electric potential, and voltage. Gauss’ Law is discussed as it relates to the electric field, induction, and the Faraday cup. The capacitance in Q = CV is used to explain charge sharing. RC decay is discussed as it relates to ESD discharge from humans, devices, wrist straps, and materials. After completing this course, the attendee should leave with a proper understanding of the differences among the calculations for peak current, power, energy, and threshold voltage for a simple device.

DD203: Designing ESD Protection for RF and mmWave CMOS Circuits

1:00 p.m. - 2:30 p.m.
Dimitri Linten, imec

Providing ESD protection for high performance RF and mmWave circuits is a very challenging task where both the expertise of a skilled RF designer and ESD designer need to be combined. This course will introduce the challenges and solutions for providing ESD protection for both narrow and wideband RF and mmWave circuits. The tutorial will not only discuss ESD devices used in RF applications, but also explore the useof ESD devices in RF circuit demonstrators. Next to the ESD techniques, RF design techniques and tools will be introduced to ESD designers. The audience will be able to understand the challenges from both RF and ESD point of view. They will have a clear overview of the solutions that are available in the public domain, and will get experience based on real design examples that will be discussed during the course. The tutorial will not be limited to ESD device design for RF, but will be more focused on how to use the components in a real RF design integration flow.

NEWDD317: ESD Challenges in Advanced FinFET and Gate-All-Around Nanowire CMOS Technologies

3:00 p.m. - 4:30 p.m.
Shih-Hung Chen, imec 

Bulk FinFET has been a mainstream CMOS technology in sub-20 nm nodes because of improved channel electrostatic and leakage control. ESD reliability has been investigated in bulk FinFET and is strongly impacted by newly introduced process options in these advanced technologies. The process options include self-align double patterning (SADP) lithography, local interconnect (LI) defined contact scheme, and S/D epitaxial growth in different process modules. The process options have impacts on ESD failure level, clamping voltage and turn-on efficiency. In addition, higher supply voltages (e.g., 1.8 volts or 3.3 volts) are still required in I/O interface circuits and some analog circuits in bulk FinFET technologies. The I/O transistors concerning latch-up (LU) prevention are also influenced by the specific process options in sub-20 nm nodes. Next to the FinFET technology, a gate-all-around (GAA) nanowire (NW) technology is a promising candidate for sub-10 nm nodes. This new device architecture will also bring impacts on ESD device characteristics. In this tutorial, we will look at the influence of the device architectures and the corresponding process options on ESD device characteristics in the FinFET/GAA NW technologies. 3D TCAD simulations bring an in-depth physical understanding of the ESD current conduction and failure mechanism in the ESD protection devices.

After this tutorial the attendees will have a clear picture of:

  • The process options in the FinFET and GAA NW technologies
  • The process options impact ESD device characteristics
  • The process options impact LU immunity
  • The ESD challenges in future CMOS technology nodes


TUTORIALS: Thursday, September 14

FC390: Basics of ESD Process Assessment

8:00 a.m. - 4:30 p.m.
Reinhold Gaertner, Infineon Technologies; Wolfgang Stadler, Intel Deutschland GmbH

This tutorial gives an introduction to the approach and measurement methodologies for ESD process assessment and ESD risk analysis in typical production processes in semiconductor, printed-circuit board (PCB), and electronic system manufacturing industries. It summarizes the relevant physical parameters (e.g., resistance, charge, electric fields, capacitances, resistances, discharge currents, and ESD event detection by EMI) and discusses their influence on the ESD risks caused by charged personnel, charged devices and boards, and ungrounded conductors. Measurement techniques are explained in detail together with their limitations for the different process steps and strategies for an efficient ESD risk assessment. The application of those measurement techniques to assess possible ESD risks and to solve ESD problems are explained using theoretical and real-world case studies from each of the processes mentioned above. Examples of possible mitigation strategies are discussed with the attendees. The tutorial includes practical demonstrations and a hands-on session for the attendees to get experience and learn pitfalls of the most important measurement techniques used in ESD process assessment.

NEWDD260: Design for EOS Reliability

8:30 a.m. - 12:00 p.m.
Charvaka Duvvury, ESD Consulting, LLC

During the design of on-chip protection and latch-up immunity, the consequences to EOS damage susceptibility are often overlooked. This class aims to first clearly establish the nature of EOS and some of the common causes for unintended EOS, followed by the on-chip IC design styles that can lead to EOS damage and customer returns. By way of illustrative examples and case studies, these potential issues are highlighted. These include the designs in low voltage CMOS, mixed voltage technologies, analog designs, and high voltage designs. Some mention of automotive applications leading to EOS and the automotive perspective will also be covered.  Finally, the design rules to follow for EOS mitigation; as well as on-going communication tips with customers to achieve these objectives, will be reviewed.

The course aims to give a clear understanding of EOS events, the definition of EOS related to on-chip design principles, design improvements to overcome EOS return rates, check lists for EOS avoidance, and tips for customer communications.

FC210: ESD Standards Overview for the Program Manager

8:30 a.m. - 12:00 p.m.
David E. Swenson, Affinity Static Control Consulting, LLC

Certification: PrM

Currently, many EOS/ESD Association standards and standard test methods are discussed in depth in the individual tutorials related to the specific subject matter. This standards tutorial provides an overview of all of the standards, grouped into common test types, based on measurement probe and test instruments. A common methodology is used in this tutorial to cover the requirements, applications, and specifications for each standard and standard test method.

FC120: Air Ionization Issues and Answers for the Program Manager

8:30 a.m. - 12:00 p.m.
Kevin Duncan, Seagate Technologies

Certification: PrM

The first principle of ESD control is to bond all conductors together, preferably to ground. This technique works well for stationary conductive objects, but how do we control electrostatic charges on process essential insulators or conductive objects that cannot be grounded? This tutorial will explore the fundamental ESD control principles surrounding the use of ionization systems in an ESD control program plan. We will explore the benefits of ionization; discuss the different technology types and the pros and cons of each. Examples will be given demonstrating when and where ionization should be used, as well as how to measure ionizer performance. The criteria surrounding installation, safety, maintenance, and contamination concerns will be reviewed. Upon completion, you will be familiar with standardized product qualification, acceptance testing, and compliance verification test methods and practices.

DD220: Transmission Line Pulse (TLP) Basics and Applications

1:00 p.m. - 4:30 p.m.
Evan Grund, Grund Technical Solutions, Inc.

Certification: DD

This tutorial will cover the basics of TLP including underlying theory, the types of TLP systems available, and how I-V curves are extracted from TLP pulses. The tutorial uses examples to show how fundamental device parameters can be measured with TLP. These parameters allow the ESD engineer to understand a technology’s properties which can be used to design successful ESD protection circuits. The student will gain an understanding of the purpose of TLP measurements, how TLP relates to HBM and CDM, fundamentals of how TLP systems work, including impedance and reflections, types of TLP systems, importance of load lines, adaptive ranging, TLP calibration, time dependence from TLP, and biased TLP measurements. The tutorial will present examples of TLP use for nMOS transistors, diodes, oxides/capacitors, and power supply clamps, as well as time dependent TDR-O and VF-TLP examples.

NEW - FC262: Electrical Fields and Particles - Practical Considerations for the Factory

1:00 p.m. - 4:30 p.m.
David E. Swenson, Affinity Static Control Consulting, LLC

ANSI/ESD S20.20 recommends that process essential insulators with a measured electrical field strength of >2000 volts at 1 inch should be kept a minimum of 12 inches from ESD susceptible items. In addition, for close proximity or contact, the standard requires that insulators have an electric field of
<125 volts at 1 inch. Just what are the practical considerations of these statements? What is the size of a charged object and magnitude of an electric field that imposes a real risk? The goal of this tutorial is to show, by demonstration, the field strength and resulting induction ability from different sized objects.

Electric fields are the major contributor (beyond gravity) to attraction of particles to surfaces. The science of particle attraction, adhesion and particle removal is very complex but it is important to have a fundamental understanding if your production processes involve cleanliness of surfaces. This tutorial will cover the important considerations of particle dynamics. 

The audience should gain a practical perspective of size and distance as related to charged objects, electrical fields, induction, and the interaction of electric fields with airborne particles.

FC110: Cleanroom Considerations for the Program Manager

1:00 p.m. - 4:30 p.m.
Chris Long, IBM

Certification: PrM

Cleanrooms and clean environments are enabling technologies required for the manufacturing of many products that have exacting contamination control requirements in order to achieve defined yield and reliability targets. Clean manufacturing is required in the semiconductor, hard disk drive, flat panel display, and pharmaceutical industries, to name a few. Requirements of cleanroom and clean environments, and tooling therein, result in low humidity levels, low surface contamination levels, use of process-required insulators, and a lack of natural ions in the controlled environment. These factors can contribute to the development of elevated static charge levels in close proximity to sensitive products, presenting both a contamination and electrostatic discharge exposure.

This tutorial will provide a detailed review of the following concepts:

  • Cleanroom and clean environment function
  • Airborne particle classification standards
  • Cleanroom compliance monitoring test methodologies
  • Electrostatic attraction relation to airborne and surface contamination
  • Electrostatic discharge concerns
  • Cleanroom static charge generation challenges and control methodologies
  • In addition, several case studies of static charge control issues in clean environments will be presented.

DD381: Electronic Design Automation (EDA) Solutions for ESD

1:00 p.m. - 2:30 p.m.
Michael Khazhinsky, Silicon Laboratories, Inc.

The verification of ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher pin-counts, and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another; across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves,  may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the recently released ESDA technical report ESD TR18.0-01-15 (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development.

DD382: Electronic Design Automation (EDA) Solutions for Latch-up

3:00 p.m. - 4:30 p.m.
Michael Khazhinsky, Silicon Laboratories, Inc.

The verification of latch-up protection networks in modern integrated circuits is a difficult challenge. There are several factors including increasing design and process complexity, higher-pin counts, and the overall computational difficulties in dealing with large data sets. Traditional latch-up geometrical rule checks using DRC tools can only provide limited verification. These checks are typically focused on layout topology. However, electrical information for latch-up risk areas throughout the chip is not readily available. While DRC checks are still useful at early design stages, relying on conventional DRC latch-up checking exclusively, poses a significant risk of missing hidden latch-up pitfalls. Consequently, a fully automated latch-up rule checking approach analyzing electrical information is highly desired.

In this tutorial we will review a typical latch-up prevention flow. Then ,the dual DRC and Calibre PERC-based latch-up verification flow will be shown. We will then provide an example of identifying latch-up injectors and describe how this information could be used in both a DRC and Calibre PERC based verification flows. Afterwards, the tutorial will introduce the concept of context based checking as it applies to latch-up spacing checks. An example of validating latch-up prevention techniques for the devices in grounded nwell will be shown along with additional latch-up verification case studies related to guard rings and well ties.