Submission Instructions

To submit your poster abstract, upload your file using the form at the bottom of the page. The submission is in PowerPoint format and is no longer than 6 slides. Please find the submission template below. Submissions are due October 12, 2020. There will be no published proceedings of IEW. Walk-on posters are also permitted at IEW with no prior review, but only those works which are submitted for review and acceptance will be included in the five-minute teaser presentation sessions.

Submission Template


ESD Soft Failures

The shrinking feature size of ICs and the increasing complexity of electronic systems lead to a higher susceptibility to soft fail- ures, such as unwanted bit errors, application crashes and system resets. Evaluation of the robustness against ESD/EMC/EMI induced malfunction is not easy. Finding the root cause of soft failures can be time-consuming. Exchange your evaluation method- ologies, test strategies, root cause analyses and best practices with other ESD experts.

Challenge of fully depleted SOI technology

Fully depleted SOI is a technology with underutilized capacities. It offers a path to downscaled, high performance RF circuits and high gate density. Yet, its ESD features have not been widely considered in the literature. Also the unexpected feature of latch-up in a SOI technology due to the back gate diffusions has not been highlighted. IEW 2020 dedicates a focus to this technology ask- ing for poster contributions and offering discussion groups. Join and share your experience.


New Insights into CDM

There are discussions ongoing concerning new stress methods like the Low Impedance Contact CDM or the Capacitively Coupled TLP which are related to the CDM. What will be the challenges for future CDM testing? Is it sufficient just to look on the stress peak current only? What are the rise time requirements for CDM measurements or which kinds of packages do we have to test?

Share your experiences with the community and influence the development of new methodologies.


Other topics and areas to consider for abstract submissions including but not limited to:

Anomalous/Unresolved ESD Issues

Random and unrepeatable ESD failures, case histories,

ESD tester correlation issues, and unique window failures.


ESD Big Data

Summarizing and viewing large ESD and latch-up tester datasets. Mapping design data to ESD and latch-up test programs.


System-Level ESD Issues

On- and off- chip IEC protection clamps, component/sys- tem ESD co-design case studies, cable discharge clamps, transient latch-up, design of system-level clamp circuits, system-level ESD test issues and scan techniques, and ESD-induced soft errors.


Failure Analysis Techniques

Locating failure sites, in particular for CDM, imaging techniques, correlating FA identified damage site with ESD stress, distinguishing EOS-like failures from ESD failures, and unusual failure modes.


EDA Tools

EDA verification and simulation tools; techniques, de- sign-flows, best practices, experiences with foundry rule decks, commercial tools, and custom tooling.


Electrical Overstress (EOS)

Root-cause analysis on a failure with an electrical induced physical damage (EIPD) signature, methodology for defin- ing AMR for a product and verifying it for different times- cales, and case studies identifying EOS damage mecha- nisms and the ensuing physical evidence.


ESD Control

ESD protection targets versus ESD control measures


Novel On-Chip Protection Clamps and Circuit Configurations

New clamp devices and clamp configurations, methods to increase the failure threshold of protected devices, high voltage clamps for automotive and power amplifiers, new chip protection concepts, and low-capacitance clamps for RF and high speed interfaces.


ESD Test Characterization, Methods, and Issues

TLP & VF-TLP debug and device characterization methods, correla- tion of TLP & VF-TLP tests with standard qualification tests, HBM and CDM tester artifacts, unresolved test results and failures, issues re- lating test qualification levels to real-world exposure, test chip meth- odology, cable discharge test methods, and test standards issues.


Technology Integration Issues

ESD sensitivity with technology transfers, 3D IC ESD design issues, qualification challenges for different fabs, unusual problems of pro- cess interaction with ESD, process monitor methods, and technology scaling issues.


Contact Information

Abstract Submission