Date & Time:
September 14, 2024
Peppermill Resort and Casino
2707 South Virginia Street, Reno, NV 89502
iStock 892252488 v2


Introduction to On-Chip ESD Protection


The tutorial is designed to provide a comprehensive understanding of electrostatic discharge (ESD) events and its implications on semiconductor devices. The tutorial will delve into the fundamentals of ESD, including the physics behind the electrostatic build-up and discharge processes. Integrated circuits can get damaged by ESD events during manufacturing, testing or in assembly when they are handled by people or machines. IC layout engineers can influence the robustness of their circuits by applying guidelines and tricks. Participants will explore various ESD protection strategies and design methodologies used in modern integrated circuits (ICs). The material will cover ESD devices used from basic CMOS to advanced FinFET technologies. The session will cover key topics such as on-chip ESD protection device structures and layout considerations, Through a blend of theoretical knowledge and practical examples, the tutorial aims to equip attendees with the skills necessary to understand on-chip ESD protection schemes. This tutorial is ideal for IC engineers seeking to enhance their expertise in ESD protection for semiconductor devices.   

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