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SP5.4.1

ANSI/ESD SP5.4.1-2017

ESD Association Standard Practice for For Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits- Transient Latch-up Testing Device Level

This document addresses steps which are required to perform transient latch-up (TLU) characterization under well-defined conditions. It defines pre-conditioning of the device-under-test (DUT), applying the stress pulse, detecting latch-up, and determining failure criteria. Additionally, a procedure to verify the test equipment is described. The test methods enable the user to perform an application specific TLU characterization with reliable and verified test set-ups.

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