Asia Online Forum Circuit Design Engineers Certification (ECEC 1)
- Date & Time:
- May 19-20, 2026
- Location:
- Virtual
Overview
Cost 680 USD
Certification online $250
The EOS/ESD Association’s ESD for Circuit Design Engineers Certification provides the circuit design engineer with the knowledge and the skills to implement ESD protection circuits and latch-up mitigation on their integrated circuit (IC) designs using industry-proven best practices.
Learning Objectives:
Upon completion of this training, engineers will be able to:
- Understand basic ESD circuits and how to implement them successfully into their product designs.
- Knowledge of basic ESD physics and how this can impact other circuit components.
Target Audience:
Circuit designers who implement ESD circuits into the product padrings and architecture
Agenda May 19, 2026
|
India (IST) |
Vietnam/Thailand (ICT) |
Singapore/China/PH/MY (SGT/CST/PST/MYT) |
Eastern USA (EDT) |
Session |
Description |
|
11:00–11:05 AM |
12:30–12:35 PM |
1:30–1:35 PM |
1:30–1:35 AM |
Welcome & Opening |
Brief introduction and overview |
|
11:05–11:50 AM |
12:35–1:20 PM |
1:35–2:20 PM |
1:35–2:20 AM |
Session 1 (45 min) |
Background of ESD Basics and Models |
|
11:50–12:00 PM |
1:20–1:30 PM |
2:20–2:30 PM |
2:20–2:30 AM |
Q&A 1 (10 min) |
Question and answer session |
|
12:00–12:45 PM |
1:30–2:15 PM |
2:30–3:15 PM |
2:30–3:15 AM |
Session 2 (45 min) |
ESD Factory Basics for Design Engineers |
|
12:45–12:55 PM |
2:15–2:25 PM |
3:15–3:25 PM |
3:15–3:25 AM |
Q&A 2 (10 min) |
Question and answer session |
|
12:55–1:10 PM |
2:25–2:40 PM |
3:25–3:40 PM |
3:25–3:40 AM |
Open Discussion Breakout 1 (15 min) |
Interactive breakout |
|
1:10–1:25 PM |
2:40–2:55 PM |
3:40–3:55 PM |
3:40–3:55 AM |
Full Break (15 min) |
Standard rest and refresh break |
|
1:25–2:10 PM |
2:55–3:40 PM |
3:55–4:40 PM |
3:55–4:40 AM |
Session 3 (45 min) |
ESD System Level Basics |
|
2:10–2:20 PM |
3:40–3:50 PM |
4:40–4:50 PM |
4:40–4:50 AM |
Q&A 3 (10 min) |
Question and answer session |
|
2:20–3:05 PM |
3:50–4:35 PM |
4:50–5:35 PM |
4:50–5:35 AM |
Session 4 (45 min) |
ESD EDA Verification Tools |
|
3:05–3:15 PM |
4:35–4:45 PM |
5:35–5:45 PM |
5:35–5:45 AM |
Q&A 4 (10 min) |
Question and answer session |
|
3:15–4:00 PM |
4:45–5:30 PM |
5:45–6:30 PM |
5:45–6:30 AM |
Session 5 (45 min) |
ESD Compact Models and Simulation |
|
4:00–4:10 PM |
5:30–5:40 PM |
6:30–6:40 PM |
6:30–6:40 AM |
Q&A 5 (10 min) |
Question and answer session |
|
4:10–4:25 PM |
5:40–5:55 PM |
6:40–6:55 PM |
6:40–6:55 AM |
Open Discussion Breakout 2 (15 min) |
Final interactive discussion and reflections |
Agenda May 20, 2026
|
India (IST) |
Vietnam/Thailand (ICT) |
Singapore/China/PH/MY (SGT/CST/PST/MYT) |
Eastern USA (EDT) |
Session |
Description |
|
11:00–11:05 AM |
12:30–12:35 PM |
1:30–1:35 PM |
1:30–1:35 AM |
Welcome & Opening |
Brief introduction and overview |
|
11:05–11:50 AM |
12:35–1:20 PM |
1:35–2:20 PM |
1:35–2:20 AM |
Session 1 (45 min) |
Basics of ESD and Latch-up Device Physics |
|
11:50–12:00 PM |
1:20–1:30 PM |
2:20–2:30 PM |
2:20–2:30 AM |
Q&A 1 (10 min) |
Question and answer session |
|
12:00–12:45 PM |
1:30–2:15 PM |
2:30–3:15 PM |
2:30–3:15 AM |
Session 2 (45 min) |
ESD Circuit-Chip Design Implementation (with Layout Principles) CMOS |
|
12:45–12:55 PM |
2:15–2:25 PM |
3:15–3:25 PM |
3:15–3:25 AM |
Q&A 2 (10 min) |
Question and answer session |
|
12:55–1:10 PM |
2:25–2:40 PM |
3:25–3:40 PM |
3:25–3:40 AM |
Open Discussion Breakout 1 (15 min) |
Interactive breakout |
|
1:10–1:25 PM |
2:40–2:55 PM |
3:40–3:55 PM |
3:40–3:55 AM |
Full Break (15 min) |
Standard rest and refresh break |
|
1:25–2:10 PM |
2:55–3:40 PM |
3:55–4:40 PM |
3:55–4:40 AM |
Session 3 (45 min) |
ESD Circuit-Chip Design Implementation (with Layout Principles) Mixed-Signal High-Voltage |
|
2:10–2:20 PM |
3:40–3:50 PM |
4:40–4:50 PM |
4:40–4:50 AM |
Q&A 3 (10 min) |
Question and answer session |
|
2:20–3:05 PM |
3:50–4:35 PM |
4:50–5:35 PM |
4:50–5:35 AM |
Session 4 (45 min) |
ESD Latch-up Product Testing Basics |
|
3:05–3:15 PM |
4:35–4:45 PM |
5:35–5:45 PM |
5:35–5:45 AM |
Q&A 4 (10 min) |
Question and answer session |
|
3:15–4:00 PM |
4:45–5:30 PM |
5:45–6:30 PM |
5:45–6:30 AM |
Session 5 (45 min) |
ESD Latchup Failures Troubleshooting Techniques and Case Studies |
|
4:00–4:10 PM |
5:30–5:40 PM |
6:30–6:40 PM |
6:30–6:40 AM |
Q&A 5 (10 min) |
Question and answer session |
|
4:10–4:25 PM |
5:40–5:55 PM |
6:40–6:55 PM |
6:40–6:55 AM |
Open Discussion Breakout 2 (15 min) |
Final interactive discussion and reflections |
Courses
|
Title |
Abstract |
Instructors |
|
Background of ESD basics and models |
This class introduces the basics of ESD: what it is, why it is a problem, and how to test for it. A basic overview of CDM, HBM, HMM, TLP, and system ESD test methods is also presented. |
John Kinnear |
|
Basics of ESD and Latch-up device physics |
The primary goal of this class is to determine the ESD Design/Operation window, i.e. the electrical boundary within which an ESD protection will meet both functional and ESD requirements. Relevant electrical parameters leading to the ESD Design Window are specified and reviewed for any class of components. Latch-up basics is also covered. |
Gianluca Boselli |
|
ESD circuit-chip design Implementation (with Layout principles) CMOS |
This class first provides an overview of prevalent ESD failure modes and the available ESD protection building blocks including diodes and transient-triggered active MOSFET clamps. The concept of an “ideal ESD clamp” is described from the perspective of an IC’s operating and failure voltage levels and the expected ESD current level. The next section discusses application scenarios for IO pad protection, distinguishing between rail-based and pad-based protection methods, and showing how the protected circuitry may participate in an ESD event. Preferred rail clamp and busing schemes for IO pad banks, including embedded analog pad domains, are introduced. The CDM response of an IO pad is used as an example for performing ESD network simulations. The concepts of secondary input protection and cross-domain CDM protection are described. The class continues with discussing the potential IC performance impact of added ESD devices and how to minimize it - a GHz LNA receiver is used as an example. The final section describes potential pitfalls of ESD designs and how to avoid them systematically. |
Gianluca Boselli |
|
ESD Circuit/Chip Design Implementation (with Layout principles): |
The primary goal of this class is to review and provide the fundamental design notions of the ESD protection solutions that will satisfy the ESD Design Window to meet both functional and ESD requirements. |
Gianluca Boselli |
|
ESD EDA Verification Tools |
The verification of ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher-pin counts and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another, across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves, may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the ESDA Technical Report TR18.0-01-14 (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development. |
Michael Khazhinsky |
|
ESD compact models and simulation |
Make designer aware of ESD-specific SPICE simulation tasks, including simulation test benches, setup and model limitations. Align with ESDA WG18 recommendations. |
Michael Khazhinsky |
|
ESD/Latchup Product Testing Basics |
This course will present a basic overview of ESD/latchup product testing and debug. Background on the test models/methods, inputs needed for the test lab for job submissions and some common pitfalls will be reviewed. |
Robert Gauthier |
|
ESD/Latchup failures troubleshooting techniques and case studies |
This course will give a basic overview of the possible failure analysis techniques to utilize on a product when an ESD or latchup failure or improvement to the product is needed. High level overview of the different types of failure analysis and which one is typically best for which failure will be reviewed. |
Robert Gauthier |
|
ESD Factory Control Basics |
This course will provide the design engineer with the basic understanding of ESD control for safe handling of ESD sensitive devices. It will give the rationale for the engineer to implement ESD safe handling practices and controls in the engineering characterization lab. |
John Kinnear |
|
ESD System Level Basics |
Based on the understanding of the interaction between board and IC level protection also using SEED simulations , the circuit designer will be able to optimize the on chip protection for interfaces exposed to residual stress of system level ESD. |
John Kinnear |
Biographies:
Gianluca Boselli completed his PhD at the University of Twente, The Netherlands, in 2001 and joined Texas Instruments, Inc., Dallas, Texas, where he focused on ESD and latch-up development for advanced CMOS technologies. He is currently managing the corporate ESD Team and he is the Director of Advanced Technology Development University Research Program. He authored several papers in the area of ESD and latch-up. Dr. Boselli has been the recipient of the best paper award on behalf of Microelectronics Reliability Journal in 2000. He received the best paper award at the EOS/ESD Symposium 2002. He also received the Outstanding Symposium award at the EOS/ESD Symposium in 2002, 2006, and 2010. In 2019 he was the recipient of the Outstanding Contribution Award, the most prestigious award granted by ESD Association. Dr. Boselli is an IEEE senior member and holds over twenty patents with several pending.
John T. Kinnear, Jr. (Auditor, Technical Reviewer)
John graduated from University of Buffalo with a BS in Electrical Engineer and a Masters in Electrical Engineering from Syracuse University. John was hired by IBM where he worked for 46 years. As part of his role, John was the Subject Matter Expert in ESD control for IBM. This included developing and implementing ESD control processes at all the IBM manufacturing sites as well as assessing IBM’s suppliers for ESD control. The processes included wafer fab to large servers with all the processes required in between.
John has been a part of the ESD Association for over 30 years. He is currently chair of Working Group 20 which is responsible for ANSI/ESD S20.20, Development of an Electrostatic Discharge Control Program. John is also a member of various other standards working groups. He is also a founding member of the Technical Advisory Support Committee (TAS) which oversees all the ESD Association standards.
John is the chair of the International Electrotechnical Commission (IEC) Technical Committee 101 on electrostatics. John is also the project leader for IEC 61340-5-1 – Electrostatic Discharge Control Program. Before becoming the chair, John was the chief delegate for the United States.
Robert Gauthier joined IBM in Essex Junction, Vermont in 1995; where he focused on device design and TCAD simulations designing devices in 0.35um technologies. In 1998, he expanded his role within IBM to also look at ESD and latchup devices in 0.25um and beyond. From 1998 through 2003 he worked on 0.25um-0.13um technologies getting heavily involved in ESD and latchup. In 2004 he became an R&D manager at IBM with emphasis on ESD/latchup development and RF modeling. From 2004-2015 he continued to manage the ESD/latchup team inside IBM along with various other functions such as TCAD. In 2015 he and the majority of his team joined GlobalFoundries during an acquisition where from 2015- 2020 he has led the worldwide ESD/latchup team within GlobalFoundries including folks in the US, Dresden and in Singapore. He has over 285 issued patents with many others filed, he has >50 publications at major conferences and journals. He has served on the ESDA BoD in the past and is currently on the ESDA BoD, he is also currently an active member on the ESDA EXCOM team. He was one of the founders of the International ESD Workshop (IEW) and is a former General Chair of the EOS/ESD Symposium.
Dr. Michael G. Khazhinsky is a Principal ESD engineer at Silicon Labs in Austin, Texas. Prior to joining Silicon Labs, he was employed at Motorola and Freescale Semiconductors, where he managed TCAD development and ESD/latch-up protection solutions for emerging process technologies, with an emphasis on ESD-EDA. Michael holds an M.S.E.E. and M.S. in Physics from the Moscow State Institute of Electronic Engineering, and a Ph.D. in Physics from Western Michigan University. Michael chairs the ESDA Working Group 18 on EDA. He has been involved in several Technical Program Committees including IRPS, IEW, ESREF, EMC, ISTFA, IPFA, and EOS/ESD Symposium. Furthermore, he has chaired the International ESD Workshop and held roles such as Workshop Chair, Technical Program Chair, Vice General Chair, and General Chair of the EOS/ESD Symposium. Michael has co-authored over 60 papers and delivered numerous invited talks on ESD, EDA, process/device TCAD, and photonic crystals. He has received seven "Best Paper" and "Best Presentation" awards from the EOS/ESD Symposium and SOI Symposium, along with the Industry Pioneer Recognition Award for his contributions to ESD EDA verification. Michael holds eighteen patents related to ESD design. He is a Senior Member of IEEE and the Vice President of the ESD Association, responsible for international conferences and events.
Future Events
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2026
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July 20-21, 2026
Forum
Virtual
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