ESD For Circuit Design Engineers Certification (ECEC 1)

Title

  Runtime

Abstract

Learning Outcome

Background of ESD basics and models

35 minutes

This class introduces the basics of ESD: what it is, why it is a problem, and how to test for it. A basic overview of CDM, HBM, HMM, TLP, and system ESD test methods is also presented.

After completing this course you will understand how static electricity is generated and why it is problematic for integrated circuits. You will also have a high-level understanding of factory control techniques as well as the test methods used to characterize ICs for robustness to ESD. This course will give the foundation needed for success in more advanced ESD courses.

Basics of ESD and Latch-up device physics

35 minutes

The primary goal of this class is to determine the ESD Design/Operation window, i.e. the electrical boundary within which an ESD protection will meet both functional and ESD requirements.  Relevant electrical parameters leading to the ESD Design Window are specified and reviewed for any class of components. Latch-up basics is also covered.

The student will understand how an ESD window is defined and how to design ESD protection devices to operate within that window after completing this course. They will understand basic latch-up physics in CMOS devices and how to prevent it. Basic knowledge of the physics of snapback in CMOS and high-voltage technologies will also be learned. Finally, they will understand some of the basics of parasitic effects of passive devices.

ESD circuit-chip design Implementation (with Layout principles) CMOS

30 minutes

This class first provides an overview of prevalent ESD failure modes and the available ESD protection building blocks including diodes and transient-triggered active MOSFET clamps. The concept of an “ideal ESD clamp” is described from the perspective of an IC’s operating and failure voltage levels and the expected ESD current level. The next section discusses application scenarios for IO pad protection, distinguishing between rail-based and pad-based protection methods, and showing how the protected circuitry may participate in an ESD event. Preferred rail clamp and busing schemes for IO pad banks, including embedded analog pad domains, are introduced. The CDM response of an IO pad is used as an example for performing ESD network simulations. The concepts of secondary input protection and cross-domain CDM protection are described. The class continues with discussing the potential IC performance impact of added ESD devices and how to minimize it - a GHz LNA receiver is used as an example. The final section describes potential pitfalls of ESD designs and how to avoid them systematically.

The goal of this course is to choose and implement ESD protection solutions most suitable for advanced CMOS integrated circuits (ICs) based on the understanding of the main ESD failure modes. This class is intended for those already familiar with CMOS devices and basic analog circuit design. Upon completion of this course, participants will be able to build ESD protection that does not impede on the voltage operating range or the performance requirements of an IC. Various application scenarios and potential design pitfalls are being discussed to enable participants to entertain a wide range of possible ESD protection solutions.

ESD Circuit/Chip Design Implementation (with Layout principles):
Mixed-Signal/High-Voltage

30 minutes

The primary goal of this class is to review and provide the fundamental design notions of the ESD protection solutions that will satisfy the ESD Design Window to meet both functional and ESD requirements.

After completion of this course, a student would gain an overview about the most commonly used protection elements, with their respective features, advantages and disadvantages, learn about the challenges of mixed voltage design, understand some of the principles of ESD protection integration: π-Network, ballasting, star-point or rail-based concepts and gain awareness on relevant layout aspects that need to be considered in the ESD design implementation.

ESD EDA Verification Tools

32 minutes

The verification of  ESD protection networks in modern integrated circuits is a difficult challenge due to increasing design and process complexity, higher-pin counts and the overall computational difficulties in dealing with large data sets. Most chips today are segmented into multiple power domains, where ESD currents must necessarily be shunted from one domain to another, across multiple-layer interconnect paths that span major portions of the chip. Furthermore, circuit blocks that are traditionally not associated with the I/O ring and which may be far from the I/O circuits themselves,  may become damaged as a result of the high voltages and currents produced during an ESD discharge. Relying on manual verification alone poses a significant risk of missing hidden ESD pitfalls. Consequently, automated ESD and latch-up rule checking is highly desired. An optimum verification flow should provide broad and flexible design rule coverage and allow incremental verification as a design progresses to avoid late-stage changes just before tape out. The integration of ESD checking tools into the standard design flow allows these rules to be used directly by IC designers to identify and correct most ESD issues prior to meeting with the ESD experts. This tutorial will outline the essential requirements of the ESD electronic design automation (EDA) verification flow which would be aligned within the IC design community, as discussed in the ESDA Technical Report TR18.0-01-14 (ESD Electronic Design Automation Checks). The tutorial will give an overview of existing ESD EDA solutions across industry, including both commercial and in-house EDA tools and flows for automated ESD checks and will discuss directions for future ESD EDA tool development.

After completion of this tutorial, a student should know basic ESD verification approaches. Student will become familiar with ESD EDA tools on the market and verification problems they can solve. Student will learn basic algorithms to start developing their own ESD verification decks. 

ESD compact models and simulation

30 minutes

Make designer aware of ESD-specific SPICE simulation tasks, including simulation test benches, setup and model limitations. Align with ESDA WG18 recommendations.

Upon completion of this course, the student will have a basic understanding of the various modeling techniques used for modeling and then simulating the ESD event. The student will also understand the basics of setting up simulation test benches to simulate the ESD event.

ESD/Latchup Product Testing Basics

40 minutes

This course will present a basic overview of ESD/latchup product testing and debug.  Background on the test models/methods, inputs needed for the test lab for job submissions and some common pitfalls will be reviewed.

Completion of this course will aid Circuit Design engineers understanding of ESD standards HBM (Human Body Model) and CDM (Charged Device Model) along with the Latch-up standard. Understanding of the stress tests will allow the designer to set the levels necessary for their circuits to survive throughout the process of manufacture and service in the field.

ESD/Latchup failures troubleshooting techniques and case studies

40 minutes

This course will give a basic overview of the possible failure analysis techniques to utilize on a product when an ESD or latchup failure or improvement to the product is needed.  High level overview of the different types of failure analysis and which one is typically best for which failure will be reviewed.

After completing this course, the circuit designer will have a foundational understanding of troubleshooting techniques which can be used to identify root-causes of ESD and Latchup failures.  These techniques include practices for evaluating the circuit from ESD and Latchup perspectives, background on analysis tools/techniques, and insights into high-level troubleshooting strategies.  These techniques are then show-cased in a series of case-studies, which will deepen the designer’s understanding.

ESD Factory Control Basics

40 minutes

This course will provide the design engineer with the basic understanding of ESD control for safe handling of ESD sensitive devices. It will give the rationale for the engineer to implement ESD safe handling practices and controls in the engineering characterization lab.

. The design engineer would be able to acquire the following skills after this course:
• Have the basic ESD knowledge required to understand concepts required for ESD control
• Be able to implement ESD controls required for the engineering characterization lab
• Understand the components required for a good ESD control program
• Be able to identify potential HBM and CDM risks in the engineering characterization lab

ESD System Level Basics

35 minutes

Based on the understanding of the interaction between board and IC level protection also using SEED simulations , the circuit designer will be able to optimize the on chip protection for interfaces exposed to residual stress of system level ESD.

After completing the course the system designer will have the knowledge to effectively use IEC61000-4-2 and protect the system against system level ESD.