Certified Professionals

Credential ID: 52736e24ea3543dfb90500b966276a61

Credential ID: https://esdcertification.esda.org/c/d35b81917fcd4b0d8567393c0c976f36

Credential ID: 38480a6863984ad59f822778412eae61

Credential ID: https://esdcertification.esda.org/c/d8fda705742942e29ac99afe51eae8d5

May R. Morris is a dedicated professional in Electrostatic Discharge (ESD) and Latch-Up (LU) Reliability Operations at Analog Devices, Inc. (ADI). With over a decade of experience as a test engineer at Maxim Integrated, May has honed her skills in ensuring the reliability and robustness of integrated circuits (ICs). Her role involves extensive testing and analysis to prevent failures caused by ESD and latch-up events, which are critical for maintaining the high standards of quality and reliability that ADI is known for.

May holds a Bachelor's degree in Electronics Engineering from Xavier University - Ateneo de Cagayan in the Philippines. Her academic background, combined with her practical experience, has equipped her with the skills necessary to excel in her field.

In her current role, May is responsible for designing and implementing reliability tests, analyzing failure mechanisms, and collaborating with design and manufacturing teams to integrate reliability into all stages of product development. Her contributions are vital in helping ADI deliver products that meet stringent reliability requirements, ensuring customer satisfaction and product longevity.

Outside of her professional life, May has a unique and endearing passion for chickens. She enjoys spending time with her feathered friends and proudly calls herself a "crazy chicken lady".

This quirky hobby adds a fun and personal touch to her otherwise technical and demanding career.

Credential ID: ea9e239e65074a41852b8c88e5bba2e5

Credential ID: b13b8891a03d4cfd84985a9a225d217c

Mike Chaine works at Micron Technology, Inc., in Boise, Idaho, as a Section Manager in the R&D Reliability Group. He has a B.S.E.E. degree from Arizona State University and has worked at Micron since 1998. Today, he is leading the R&D Reliability Group in the area of ESD/LUP design and development, and has two engineers reporting to him. He is working in the area of On-Chip ESD protection design for all advanced DRAM and FLASH technologies. These responsibilities include ESD wafer and device level characterization analysis, ESD circuit failure analysis, and ESD design and layout rule development.

Mike has authored several papers on a variety of ESD areas ranging from ESD device test issues, ESD protection circuit analysis, and unique ESD circuit interaction phenomena. He holds more than 10 ESD patents and has several patents pending.

Mike chairs two different IC device work groups; Human Body Model (HBM) WG5.1 and Socketed Device Model (SDM) WG5.3.2.

Credential ID: 6b3002deb3894d80ac22744c80c4be1d