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PhD researcher on I/O design exploration and ESD characterization in advanced technologies with process/device/material options
Due to the geometry scaling and specific lithography features, implementing high-voltage (HV) I/O transistors may become a very challenging task in advanced gate-all-around vertically stacked horizontal nanowires (NWs) technologies. Using core transistors for HV I/O circuit design could be an alternative design solution without additional development cost of HV I/O transistors. In this I/O design exploration, the functional performance of I/O circuit will be the first challenge because of the complicated circuit architecture and transistor/circuit reliability concerns. The reliability concerns are not only related to FEOL device reliability, such as TDDB and HC degradation, but also related to Electrostatic discharge (ESD). The later one has become a major reliability concern in advanced CMOS technology and ESD robustness is always a key parameter in I/O circuit specifications. In fact, the technology roadmap has set the stage of the ESD challenges. There are two main technology options in CMOS scaling roadmap. The first one is the device architecture moving from FinFET to GAA NW. The second is the high mobility materials, such as SiGe, and Ge, integrated as the channel of the transistors in either FinFET or GAA NW. However, the technology options and complicated circuit architecture often result in significant impact on ESD robustness of the protection devices.
FEOL device reliability in static/quasi-static stress conditions has been investigated several advanced technologies [1-3]. However, in real circuit applications, the transient overshoot could bring severe overvoltage stresses which can significantly impact transistor performance and finally induce circuit performance degradation. This issue will be more pronounced in HV I/O circuit design with only core transistors. On the other hand, ESD reliability has been investigated in Si FinFET technology [4-9] and Si GAA NW  technology. It is strongly impacted by the process options and the specific device architecture [4-12]. Then, ESD characterizations of planar SiGe and FinFET SiGe technologies have been presented in our previous works [11, 12]. The SiGe quantum well channel plays an dominated role in ESD performance and the Si/SiGe heterostructure junction brings an isolation effect on carrier density and current distribution. In addition, the ESD results of the planar Ge technology and the FinFET Ge technology with the strain process option have been also shown in our previous works [13,14]. The non-destructive differential resistance lowering (DRL) was reported in Ge diodes because thermally induced carrier generation in Ge. The Ge/SiGe heterostructure junction not only induces the electrical isolation effect, but also bring the thermal isolation due to the thermal property difference in different materials. In a nutshell, the reliability challenges in I/O circuits of advanced CMOS technologies are directly from the interaction between specific process options, device architectures, the material properties, and even the circuit applications.
In this PhD program, the main tasks will focus on ESD/FEOL reliability of I/O circuit applications in advanced FinFET and GAA NW technologies. Based on the past learning, we will start the exploration of the reliability influenced by specific circuit architectures, materials and the related process and device options, such as the nano-sheet architecture and the vertical GAA NW structure.
Required background: electrical engineering (solid-sate or analog IC design field), physics, material science. Preferred: Si/compound semiconductor device physics, VLSI process/manufacturing/integration, TCAD process/device simulations, solid-state physics, layout/SPICE design environment
Type of work: 10% literature, 25% technology study, 40% experimental work, 25% TCAD simulation
Supervisor: Guido Groeseneken
Daily advisor: Shih-Hung Chen
Ref:  B. Kaczer, IEDM short course, 2016.  J. Franco, et al., IEDM Tech. Dig. 2017.  A. Chasin, et al., IEDM Tech. Dig. 2017.  S. Thijs, et al., EOS/ESD Symp., 2009, p. 76.  A. Griffoni, et al., EOS/ESD Symp., 2009, p. 59.  S. Thijs, et al., “EOS/ESD Symp., 2011, p. 27.  S.-H. Chen, et al., EOS/ESD Symp., 2013, p. 1.  D. Linten, et al., IRPS, 2013, p. 2B.5.1-8.  S.-H. Chen, et al., IEDM Tech. Dig. 2014, p. 514.  S.-H. Chen, et al., IEDM Tech. Dig. 2015, p. 362.  G. Hellings, et al., EOS/ESD symp., 2012, p. 1.  D. Linten, et al., EOS/ESD Symp., 2013, pp. 22-29.  R. Boschke, et al., EOS/ESD Symp., 2014.  R. Boschke, et al., EOS/ESD Symp., 2015.
The reference code for this PhD position is STS1712-26. Mention this reference code on your application form.
ESD, Reliability and Device physics specialist
The Cadence IP group develops integrated circuits in processes from 65n down to the industry most recent process nodes in different foundries.
As an ESD, Reliability and Device physics specialist, you will be part of a key central team responsible to support design teams across the world as they plan, design and test their IP.
You will be responsible to
- Evaluate process device models and design rules and identify potential impacts on the design of integrated circuits
- Provide design and layout best practices for performance, reliability and ESD
- Evaluate failure mechanisms and reliability risks of products during planning, development, testing and delivery phases
- Define, analyze and communicate ESD and reliability test plans
- Master’s or PhD degree in Electrical Engineering, Physics
- Strong understanding of semiconductor device physics, IC (integrated circuits) fabrication and IC design
- Strong understanding of ESD (Electro Static Discharge) in IC
- Strong communication, presentation and customer service skills
- Hands experience in the design, performance, analysis and interpretation of circuit testing
- Hands on experience with EDA tools, especially Cadence tools
For more information, contact:
Stephane Leclerc | Design Engineering Director IP Group, High Performance Phy Group, Montreal Design Center | email@example.com
Job Location: Rochester, NY
Provide Electrostatic Discharge (ESD) technical expertise in support of multiple commercial and Aerospace programs. Coordinate Electrostatic Laboratory, and actively engage in all aspects of Electrostatic testing and analysis of materials, electronic hardware and facilities, as well as personnel training and safe practices. Create plans for and provide all necessary ESD control and monitoring of high reliability hardware programs and facilities. Perform periodic audits and quarterly facility inspections
- B.S. degree with 3+ years of experience or equivalent
- Degree in Electrical Engineering or Applied Physics
- Expertise in all aspects of hardware protection from ESD, including facility requirements, personnel training programs and triboelectric charging concepts
- Experience working in cleanroom environments
- Expertise with electrostatic surface potential and field meters, resistivity meters, H.V.P.S.’s and charged-plate analyzers
- Expertise with ESD workstations, including grounding requirements, constant-monitoring devices and wrist/heel grounding straps
- Familiarity with air ionization techniques and equipment
- Familiarity with ESD Standards (ANSI/ESD, MIL-STD, ISO, ASTM)
- ESD experience in an aerospace environment
- Contamination control expertise
- Experience working near critical optical surfaces
- Project management experience
- Statistics: D.O.E., FMEA, FMECA, RCA
- PC skills: MS Office (Word, Excel, PowerPoint, Project, Math-Cad), Visio, Lotus Notes
- Strong analytical skills
- Ability to work independently as well as in functional team and project team environments
- Good verbal and written communication skills
- Comfortable making presentations and delivering training sessions
- Able to handle multiple tasks and changing priorities to meet challenging schedules
Please be aware that many of our positions require a security clearance, or the ability to obtain one. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.
For more Information or to Apply, please contact:
Space and Intelligence Systems
Ofc.: (585) 269-6006 pager: (585) 246-1942
Cell # (585) 764-2506
800 Lee Rd. P.O. Box 60488
Rochester, N.Y. 14606-0488
rm:2106 1/601 m/c 0488
NATIONAL SALES MANAGER
Male or Woman, 30- 55 (desirable)
Industrial, Electronics or Electrical Engineer (desirable)
Five years of previous experience as:
• Sales or Regional Sales Manager
• B2B Sales
• Electronics/ESD sales and its dealer network
• Knowledge of Electronics Industry
•Knowledge of General Management Processes
• Quarterly bonus depending on objectives achievement
For more information contact:
Phone: +52 01 33 30019900
Managing USA domestic sales.
Achieving financial objectives and opening markets within the electronics industry.
• Assisting the ESTATEC´S General Manager and Corporative CEO to develop the company´s introduction strategy to American market.
• Implementing that strategy with distributors.
• Planning the annual sales budget.
• Developing new customers according to the annual sales budget.
• Following up Top customers.
• Provide the attraction strategy for new customers
• Monitor the business strategy with Distributors Company.
• Solve customer complaints.
• Monitoring Billing and Collection
• Coordination of delivery and goods receipt.
• Supervision of warehouse operation and best practices
• Administration of the whole company resources.
• Resolve customer complaints about service and sales
• Solve products and service problems
• Ability to analyze
• Assertive communication
• Time management
• Customer-oriented service
• Complaints management
• MS Office
• Electronics and ESD
• Future sales forecast
• Market analysis
• Managing financial budgets