ESD Association Technical Report for Relevant ESD Foundry Parameters for Seamless ESD Design and Verification Flow – Part 2 – ESD Parameters from Intellectual Property (IP) Providers
This document is intended to highlight the ESD-related issues relevant to intellectual property (IP) selection, IP on-chip usage, and IP integration verification. It addresses best practices which are consolidated between IP providers and IP users. Latch-up rules are only addressed as far as they are related to integration of ESD protection elements.Table of Contents
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