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January 1, 2025   |By Wen-Chieh Chen To continue Moore’s law, transistor scaling needs to be enabled by geometry innovations. From the 22nm node, bulk FinFET, a multi-gate transistor built on a silicon substrate, has replaced planar…

SOIC & SOT: The Microchips: Engineers Choose the Ten Best STEM Toys to Gift January 3, 2025   |By EOS/ESD Association, Inc. Purdue University’s Engineering Education College has selected “SOIC and SOT” as the #1…

The Impact on ESD Risk of AI on Silicon Fabrication and the Implications of Increasing Memory Stacks December 1, 2024   |By James Davis, Greg O’Sullivan, Souvic Mitra, Bong Andres and EOS/ESD Association, Inc. Artificial intelligence (AI) has emerged as…

Why IS ESD Compact Modeling Important Electrostatic Discharge (ESD) is well known as one of the major reliability concerns in semiconductor manufacturing. Proper ESD protection solutions are always required to ensure integrated circuits do not fail during an ESD event.…

Is your semiconductor fab certified to S20.20? If yours is like most fabs, the answer is likely no. This is because the ESD controls needed in the front-end fabs are different from the back-end processes…

For Immediate Release EOS/ESD Association, Inc. Announces 2025 Elected Officers and Board Members September 25, 2024 ROME, NY – EOS/ESD Association, Inc. announced its elected officers and board members for 2025 at its…