EOS/ESD Association, Inc. Academia Committee

Contact:

For information regarding the Academia Committee, please contact us at info.eosesda@esda.org.

Overview

The Academia committee of the EOS/ESD Association, Inc. is working to expand university education in ESD technology across the globe and to encourage and promote research in critical areas of ESD development. We aim to get a greater exposure of ESD Technology worldwide to have an increased student population as EOS/ESD Symposium contributors, EOS/ESD Association members, and provide a mentor process to students for linkage with industry opportunities.

Objectives

Create Living Database of Academic Contacts
Provide Classroom Lecture Packets with periodic updates
Facilitate ESDA – University Contact Interface
Assist Academic Research Activities through Presentations/Mentoring

Academia Program

Over the last four decades, EOS/ESD Association, Inc. provided services through education, technical exchange of information, and facilitating venues to bring the industry together to improve methods for ESD reliability. Electrostatic Discharge (ESD) has been a pervasive reliability threat to the electronics industry. As a result, EOS/ESD Association, Inc. has provided several lectures at different universities. We are committed to offer an introduction to ESD as part of university lectures in the classroom to enhance academic understating of the phenomena in the semiconductor technologies as well as promote research interests in the subject.

This complimentary 60-minute live video recording of the basic introduction lecture was presented as an electrical engineering classroom lecture in November 2019 and is provided for general use for all university educators.

https://www.youtube.com/watch?v=FBNQL2c5mxk&

Lecture Packets

Download

Click here to download the ESD Lecture Packet.

The lecture packet contains a basic and advanced lecture.

Technology Roadmap

Download

Click here to view the EOS/ESD Association, Inc. Technology Roadmap

Capstone Project Summaries

ESD Latch-Up Capstone Project Summary

University of Arkansas – CSCE Department
Capstone II – Final Report – Spring 2025
Electrostatic Discharge Latch-Up Detection
Gavin Edens, Kile Harvey, Luke Simmons, Carl von Bergen

Abstract
When designing integrated circuits (ICs) using Complementary Metal-Oxide-Semiconductor (CMOS) technology, an important issue that must be accounted for in the design process is latch-up, an unwanted occurrence in which power and ground become shorted due to voltage differentials across terminals on a CMOS gate. A common perpetrator of this phenomenon is electrostatic discharge (ESD), in which a charge is quickly released from an outside source into the IC, thereby causing latch-up. In industry, designs are tested for their resilience to this by using test benches that force conditions that can cause latch-up.

The Electrical Engineering (EE) team that we worked with on this project was tasked with creating a board that would function similarly to the test benches used in industry for causing latch-up in designs. There is information, however, that can be obtained by collecting data about the state of the design leading up to the occurrence of latch-up, which can lead to a deeper understanding of latch-up and why it occurs.

This data is tedious to manually parse through and interpret, so we created a desktop application that receives this data from the board and presents it in a way that is easy to interpret for users of the application, along with allowing for customization of the data visualization. We also allow control of the microprocessor on the board through interfacing with the desktop app.

Click here to download the full report

Committee List

Shih-Hung Chen

AMD
Ann Concannon

Texas Instruments, Inc.
Charvaka Duvvury
Robert Gauthier

IBM
Harald Gossner

Intel
Michael Khazhinsky

Silicon Laboratories, Inc.
Prantik Mahajan

Renesas
Tim Maloney

Center for Analytic Insights
Mirko Scholz

Infineon
Dongseok Shin

Samsung
Wei-Min Wu

imec
Guangyi Lu

Southeast University