ASIA Certification Online Event ESD For Circuit Design Engineers Certification (ECEC 1)

Cost 680 USD

Certification online $250

The EOS/ESD Association’s ESD for Circuit Design Engineers Certification provides the circuit design engineer with the knowledge and the skills to implement ESD protection circuits and latch-up mitigation on their integrated circuit (IC) designs using industry-proven best practices.

Learning Objectives:

Upon completion of this training, engineers will be able to:

• Understand basic ESD circuits and how to implement them successfully into their product designs.
• Knowledge of basic ESD physics and how this can impact other circuit components.

Target Audience:

Circuit designers who implement ESD circuits into the product padrings and architecture

Agenda May 19, 2026

Agenda May 20, 2026

Biographies: 

Gianluca Boselli completed his PhD at the University of Twente, The Netherlands, in 2001 and joined Texas Instruments, Inc., Dallas, Texas, where he focused on ESD and latch-up development for advanced CMOS technologies. He is currently managing the corporate ESD Team and he is the Director of Advanced Technology Development University Research Program. He authored several papers in the area of ESD and latch-up. Dr. Boselli has been the recipient of the best paper award on behalf of Microelectronics Reliability Journal in 2000. He received the best paper award at the EOS/ESD Symposium 2002. He also received the Outstanding Symposium award at the EOS/ESD Symposium in 2002, 2006, and 2010. In 2019 he was the recipient of the Outstanding Contribution Award, the most prestigious award granted by ESD Association. Dr. Boselli is an IEEE senior member and holds over twenty patents with several pending.

John T. Kinnear, Jr. (Auditor, Technical Reviewer)

John graduated from University of Buffalo with a BS in Electrical Engineer and a Masters in Electrical Engineering from Syracuse University. John was hired by IBM where he worked for 46 years. As part of his role, John was the Subject Matter Expert in ESD control for IBM. This included developing and implementing ESD control processes at all the IBM manufacturing sites as well as assessing IBM’s suppliers for ESD control. The processes included wafer fab to large servers with all the processes required in between.

John has been a part of the ESD Association for over 30 years. He is currently chair of Working Group 20 which is responsible for ANSI/ESD S20.20, Development of an Electrostatic Discharge Control Program. John is also a member of various other standards working groups. He is also a founding member of the Technical Advisory Support Committee (TAS) which oversees all the ESD Association standards.

John is the chair of the International Electrotechnical Commission (IEC) Technical Committee 101 on electrostatics. John is also the project leader for IEC 61340-5-1 – Electrostatic Discharge Control Program. Before becoming the chair, John was the chief delegate for the United States.

Robert Gauthier joined IBM in Essex Junction, Vermont in 1995; where he focused on device design and TCAD simulations designing devices in 0.35um technologies. In 1998, he expanded his role within IBM to also look at ESD and latchup devices in 0.25um and beyond. From 1998 through 2003 he worked on 0.25um-0.13um technologies getting heavily involved in ESD and latchup. In 2004 he became an R&D manager at IBM with emphasis on ESD/latchup development and RF modeling. From 2004-2015 he continued to manage the ESD/latchup team inside IBM along with various other functions such as TCAD. In 2015 he and the majority of his team joined GlobalFoundries during an acquisition where from 2015- 2020 he has led the worldwide ESD/latchup team within GlobalFoundries including folks in the US, Dresden and in Singapore. He has over 285 issued patents with many others filed, he has >50 publications at major conferences and journals. He has served on the ESDA BoD in the past and is currently on the ESDA BoD, he is also currently an active member on the ESDA EXCOM team. He was one of the founders of the International ESD Workshop (IEW) and is a former General Chair of the EOS/ESD Symposium.

Dr. Michael G. Khazhinsky is a Principal ESD engineer at Silicon Labs in Austin, Texas. Prior to joining Silicon Labs, he was employed at Motorola and Freescale Semiconductors, where he managed TCAD development and ESD/latch-up protection solutions for emerging process technologies, with an emphasis on ESD-EDA. Michael holds an M.S.E.E. and M.S. in Physics from the Moscow State Institute of Electronic Engineering, and a Ph.D. in Physics from Western Michigan University. Michael chairs the ESDA Working Group 18 on EDA. He has been involved in several Technical Program Committees including IRPS, IEW, ESREF, EMC, ISTFA, IPFA, and EOS/ESD Symposium. Furthermore, he has chaired the International ESD Workshop and held roles such as Workshop Chair, Technical Program Chair, Vice General Chair, and General Chair of the EOS/ESD Symposium. Michael has co-authored over 60 papers and delivered numerous invited talks on ESD, EDA, process/device TCAD, and photonic crystals. He has received seven "Best Paper" and "Best Presentation" awards from the EOS/ESD Symposium and SOI Symposium, along with the Industry Pioneer Recognition Award for his contributions to ESD EDA verification. Michael holds eighteen patents related to ESD design. He is a Senior Member of IEEE and the Vice President of the ESD Association, responsible for international conferences and events.