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Transient Latch-up

ESD TR5.4-03-11 - Electronic

ESD Association Technical Report For Electrostatic Discharge Sensitivity Testing - Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing – Component Level - Supply Transient Stimulation

The information and procedures defined in this technical report may be used to search for latch-up sensitive layouts within integrated circuits. The stress levels and stimuli parameter values defined may be used for a wide range of devices.  Levels and values can be scaled up or down to suit the requirements of the actual device under test and types of transient stimuli being used.

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