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Transient Latch-up

ESD TR5.4-02-08 - Electronic

ESD Association Technical Report – Determination of CMOS Latch-up Susceptibility – Transient Latch-up – Technical Report No. 2

The information presented in this technical report covers the time period from January 2000 when the first technical report was published through the development and release of the TLU SP to present. The data contained herein represents a wide variety of hardware but is primarily based on the procedure in the SP or experiments that led to that method. Data demonstrating the latch-up effect is presented. This data is used to determine the shape of the waveform used in the test method as well as justify some of the limits for the parameters defined such as polarity, pulse width and rise-time (slew rate).

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