Industry Jobs Board
The job openings listed are a service to the industry, for current status please follow the links provided.
EOS/ESD Association, Inc. is not responsible for the content or validity of the listing.
To post a job opening contact: firstname.lastname@example.org
Job Title: ESD Design & Characterization Engineer
Location: Boise, ID
Job ID #112421
Micron Technology's vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.
The TD ESD/Latch-up Design and Characterization team at Micron Technology, Inc. is seeking an experienced ESD Engineer with emphasis conducting ESD/LUP research and experiments to investigate how to design-in the best ESD and latch-up circuit solutions for new memory designs.
Successful candidates for this position will have:
• A strong knowledge of advanced semiconductor device physics, including deep submicron CMOS devices.
• A good understanding of state-of-the-art CMOS process technology and electrical circuit analysis.
• Experience in Cadence design tools for design, layout and verification tools.
• Hands on experience in ESD characterization analysis using wafer level transmission line pulse (TLP) test equipment.
• Experience waveform generators, oscilloscopes, source/measure units, Agilent and/or Keithley parametric analyzers/testers, and impedance analyzers.
• Familiarity with ESD analysis tools like PERC or PathFinder or similar like software tools.
• Strong data analysis skills are required to extract the high current ESD properties and develops ESD/Latch-up design rules for critical ESD circuits.
• Strong oral and written communication skills is required to provide ESD/LUP technical leadership with diverse worldwide teams in Design, Product Engineering, R&D characterization, and Quality Assurance.
An MS/PhD in Electrical Engineering, Microelectronics, or related discipline. BS + minimum of 5 years of experience will also be considered. An ESD Certified Professional Design Certification from the ESD Association would be strongly desired, but is not absolutely required.
As the leader in innovative memory solutions, Micron is helping the world make sense of data by delivering technology that is transforming how the world uses information. Through our global brands - Micron, Crucial, and Ballistix - we offer the industry's broadest portfolio. We are the only company manufacturing today's major memory and storage technologies: DRAM, NAND, NOR, and 3D XPoint memory. Our solutions are purpose built to leverage the value of data to unlock financial insights, accelrate scientific breakthroughs and enhance communication around the world.
EmployeeRewards Program, Healthcare, Paid time off (combined sick-leave and vacation time), Retirement Savings Plan, Paid Maternity/Paternity Leave, Employee Assistance Program, Professional Development Training, Workplace Wellness Program, Micron Health Clinic (Boise only), Fitness Center/Activity Rooms (Boise only), Tuition Reimbursement, Micron Corporate Discounts, Casual Dress Attire.
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).
ARC Sunphotometry and Satellite (SunSat) team Instrumentation Engineer (10/9/18)
1. Background: The NASA Ames Research Center (ARC) SunSat group supports a variety of
instruments (e.g. see http://www.mdpi.com/2072-4292/5/8/3872) that perform optical
measurements of tropospheric aerosols and trace gasses when installed in NASA research
aircraft . The ARC SunSat team is funded to maintain existing instruments (2STAR, 3STAR,
4STAR) and develop the next generation instrument (5STAR). This set of instruments
(collectively termed nSTAR) depends on precision radiometer and spectrometer detectors and
include a variety of transmissive, diffractive, and diffusive optical elements, including fiber optic
light path technology. Robotics technology is required for sun tracking and sky scanning
functionality both on the ground and in flight. During flight missions the detector head is
exposed to the free stream environmental conditions up into the stratosphere.
2. Job Description: An instrumentation engineer is required to support the development of the
nSTAR instruments and various supporting instrument apparatus. Upper-division majors
pursuing degrees in electrical and mechanical engineering and recent graduates that are US
Citizens are encouraged to apply for this contractor position. Specific skills include the ability to
create, read and interpret engineering design drawings and to create the wiring and electronic
printed circuit board components, to NASA aircraft airworthiness standards. Additionally, field
engineering expertise is required to support existing instruments that are deployed in a series of
flight experiments through 2018. If not experienced, willingness to learn and adhere to NASA
aircraft airworthiness, assembly, ESD, field operations, QA, safety and other standards are
The engineer will work with the SunSat staff on design concepts and will be responsible for
developing mechanical and electrical design documents. Critical design products include
drawings, Gerber/drill files, BOM spreadsheet, STEP files, assembly instructions, etc., suitable
for procuring components and commercial fabrication services. Additionally, the engineer will
support hands-on fabrication of wiring harness and printed circuit board components using
electronics fabrication tools at ARC, and through commercial vendors.
Specific skills include:
A. CAD: SolidWorks (mechanical design and stress analysis for 5STAR design and
B. Schematic capture and printed circuit board design using EAGLE or similar software.
C. Directed support of development of precision radiometer photodiode detector-based
instrumentation including wide dynamic range amplifier circuits and data acquisition.
D. Use of benchtop electronics equipment for debugging, validation, and testing.
E. CAM: MasterCam (assist with nSTAR fabrication in building N245).
F. LabView (assist with nSTAR ADC and data acquisition programming).
G. LabView (assist with nSTAR motion control for instrument pointing and tracking).
H. MatLab (assist with stress analysis and airworthiness substantiation for nSTAR
I. Thermal Design (assist with 5STAR thermal design, re-design of 4STAR spectrometer
3. Schedule: Work may be done independently as the individual's schedule permits. Off-hours
might actually be preferred for CAD license availability. This position need not be exclusive of
other employment or educational commitments. A desk at the NASA ARC (Mountain View,
CA) in building N245 will be provided. A short meeting will be scheduled every week to discuss
design concepts, evaluate approach, and assess progress. Project schedules are expected to
require approximately 10 hours per week beginning in October 1, 2018 and extending through
September 30, 2019. More intensive work schedules up to 28 hours per week during school
breaks would be desirable.
4. Government furnished equipment: NASA will authorize contractor purchase of an
appropriate laptop with VPN and client software to access custom software licenses through
building N245 license servers.
5. Performance Standards: Milestones of accomplishment will include design reviews at
intermediate and final stages. The engineer will coordinate fabrication of mechanical parts and
wiring harness components. The primary success metric will be the successful fabrication of the
Position: ESD Contract Auditor for 3rd Party Certification
Location: Global (Asia/Pacific Region Preferred)
Summary of Position:
DEKRA is seeking an ANSI/ESD S20.20 auditor on a subcontractor basis to support their growing international client base. The position is remote location, from home office. .
Essential Duties and Responsibilities include the following.
- Maintain schedule of audits with customers.
- Maintain appropriate auditor credentials
- Perform 3rd party ANSI/ESD S20.20 audits (and other ISO audits if qualified) for DEKRA clients
- Utilize polished, professional presentation skills while assessing and presenting findings.
- Provide accurate reports in a timely manner.
- Provide timely and accurate evaluations of client corrective action and closure.
Required Knowledge, Skills, and Abilities
- Expertise with Microsoft Excel, Word, and PowerPoint.
- Must be ESD Association Certified Assessor
- Excellent interpersonal skills, verbal, written and presentation skills.
- Strong organization skills.
Required Education and Experience
- Bachelor’s degree in Mechanical or Electrical Engineering in the quality management systems industry preferred; or equivalent combination of education and experience
- Minimum of 4 years experience in quality systems management is preferred.
- 3rd party audits experience.
Send resume and credentials (or any other questions) to Sales.US@dekra.com
Corporate Process Reliability – Electrical Engineer
The Corporate Process Reliability group at Intersil Corporation is looking for a new college graduate in Electrical Engineering with educational experience in analog circuits and semiconductor devices. The chosen candidate will learn three key functions within the Technology Development Group: ESD design and characterization, wearout structure design and characterization, and device layout and modeling. The chosen candidate will support these three functions through design and electrical characterization of test structures and circuits blocks.
Location: Palm Bay, FL
1) ESD Development and Testing
- ESD test chip design and layout
- TLP and vf-TLP setup and testing
- HBM/MM ESD testing
2) Electrical Characterization
- Leakage and Capacitance Characterization of ESD
- Burn-in and radiation effect testing
- Programming and automation of lab based instruments and testers
3) Test chip schematic and layout design
4) Compact modeling of semiconductor devices
1) Bachelors/Masters in EE with emphasis in analog circuits and semiconductor devices
2) Hands on experience with lab electronic equipment including but not limited to: semiconductor parameter analyzers (SPA), source measure units (SMU), curve tracers, oscilloscopes, pulse generators, and power supplies
3) Experience bread-boarding and building experimental circuits
4) SPICE Circuit Simulation; Cadence Virtuoso a plus
5) Software programming experience; instrument control and automation a plus
6) Exposure to IC layout tools; Cadence Virtuoso a plus
For more information, contact :
PhD researcher on I/O design exploration and ESD characterization in advanced technologies with process/device/material options
Due to the geometry scaling and specific lithography features, implementing high-voltage (HV) I/O transistors may become a very challenging task in advanced gate-all-around vertically stacked horizontal nanowires (NWs) technologies. Using core transistors for HV I/O circuit design could be an alternative design solution without additional development cost of HV I/O transistors. In this I/O design exploration, the functional performance of I/O circuit will be the first challenge because of the complicated circuit architecture and transistor/circuit reliability concerns. The reliability concerns are not only related to FEOL device reliability, such as TDDB and HC degradation, but also related to Electrostatic discharge (ESD). The later one has become a major reliability concern in advanced CMOS technology and ESD robustness is always a key parameter in I/O circuit specifications. In fact, the technology roadmap has set the stage of the ESD challenges. There are two main technology options in CMOS scaling roadmap. The first one is the device architecture moving from FinFET to GAA NW. The second is the high mobility materials, such as SiGe, and Ge, integrated as the channel of the transistors in either FinFET or GAA NW. However, the technology options and complicated circuit architecture often result in significant impact on ESD robustness of the protection devices.
FEOL device reliability in static/quasi-static stress conditions has been investigated several advanced technologies [1-3]. However, in real circuit applications, the transient overshoot could bring severe overvoltage stresses which can significantly impact transistor performance and finally induce circuit performance degradation. This issue will be more pronounced in HV I/O circuit design with only core transistors. On the other hand, ESD reliability has been investigated in Si FinFET technology [4-9] and Si GAA NW  technology. It is strongly impacted by the process options and the specific device architecture [4-12]. Then, ESD characterizations of planar SiGe and FinFET SiGe technologies have been presented in our previous works [11, 12]. The SiGe quantum well channel plays an dominated role in ESD performance and the Si/SiGe heterostructure junction brings an isolation effect on carrier density and current distribution. In addition, the ESD results of the planar Ge technology and the FinFET Ge technology with the strain process option have been also shown in our previous works [13,14]. The non-destructive differential resistance lowering (DRL) was reported in Ge diodes because thermally induced carrier generation in Ge. The Ge/SiGe heterostructure junction not only induces the electrical isolation effect, but also bring the thermal isolation due to the thermal property difference in different materials. In a nutshell, the reliability challenges in I/O circuits of advanced CMOS technologies are directly from the interaction between specific process options, device architectures, the material properties, and even the circuit applications.
In this PhD program, the main tasks will focus on ESD/FEOL reliability of I/O circuit applications in advanced FinFET and GAA NW technologies. Based on the past learning, we will start the exploration of the reliability influenced by specific circuit architectures, materials and the related process and device options, such as the nano-sheet architecture and the vertical GAA NW structure.
Required background: electrical engineering (solid-sate or analog IC design field), physics, material science. Preferred: Si/compound semiconductor device physics, VLSI process/manufacturing/integration, TCAD process/device simulations, solid-state physics, layout/SPICE design environment
Type of work: 10% literature, 25% technology study, 40% experimental work, 25% TCAD simulation
Supervisor: Guido Groeseneken
Daily advisor: Shih-Hung Chen
Ref:  B. Kaczer, IEDM short course, 2016.  J. Franco, et al., IEDM Tech. Dig. 2017.  A. Chasin, et al., IEDM Tech. Dig. 2017.  S. Thijs, et al., EOS/ESD Symp., 2009, p. 76.  A. Griffoni, et al., EOS/ESD Symp., 2009, p. 59.  S. Thijs, et al., “EOS/ESD Symp., 2011, p. 27.  S.-H. Chen, et al., EOS/ESD Symp., 2013, p. 1.  D. Linten, et al., IRPS, 2013, p. 2B.5.1-8.  S.-H. Chen, et al., IEDM Tech. Dig. 2014, p. 514.  S.-H. Chen, et al., IEDM Tech. Dig. 2015, p. 362.  G. Hellings, et al., EOS/ESD symp., 2012, p. 1.  D. Linten, et al., EOS/ESD Symp., 2013, pp. 22-29.  R. Boschke, et al., EOS/ESD Symp., 2014.  R. Boschke, et al., EOS/ESD Symp., 2015.
The reference code for this PhD position is STS1712-26. Mention this reference code on your application form.
ESD, Reliability and Device physics specialist
The Cadence IP group develops integrated circuits in processes from 65n down to the industry most recent process nodes in different foundries.
As an ESD, Reliability and Device physics specialist, you will be part of a key central team responsible to support design teams across the world as they plan, design and test their IP.
You will be responsible to
- Evaluate process device models and design rules and identify potential impacts on the design of integrated circuits
- Provide design and layout best practices for performance, reliability and ESD
- Evaluate failure mechanisms and reliability risks of products during planning, development, testing and delivery phases
- Define, analyze and communicate ESD and reliability test plans
- Master’s or PhD degree in Electrical Engineering, Physics
- Strong understanding of semiconductor device physics, IC (integrated circuits) fabrication and IC design
- Strong understanding of ESD (Electro Static Discharge) in IC
- Strong communication, presentation and customer service skills
- Hands experience in the design, performance, analysis and interpretation of circuit testing
- Hands on experience with EDA tools, especially Cadence tools
For more information, contact:
Stephane Leclerc | Design Engineering Director IP Group, High Performance Phy Group, Montreal Design Center | email@example.com
Job Location: Rochester, NY
Provide Electrostatic Discharge (ESD) technical expertise in support of multiple commercial and Aerospace programs. Coordinate Electrostatic Laboratory, and actively engage in all aspects of Electrostatic testing and analysis of materials, electronic hardware and facilities, as well as personnel training and safe practices. Create plans for and provide all necessary ESD control and monitoring of high reliability hardware programs and facilities. Perform periodic audits and quarterly facility inspections
- B.S. degree with 3+ years of experience or equivalent
- Degree in Electrical Engineering or Applied Physics
- Expertise in all aspects of hardware protection from ESD, including facility requirements, personnel training programs and triboelectric charging concepts
- Experience working in cleanroom environments
- Expertise with electrostatic surface potential and field meters, resistivity meters, H.V.P.S.’s and charged-plate analyzers
- Expertise with ESD workstations, including grounding requirements, constant-monitoring devices and wrist/heel grounding straps
- Familiarity with air ionization techniques and equipment
- Familiarity with ESD Standards (ANSI/ESD, MIL-STD, ISO, ASTM)
- ESD experience in an aerospace environment
- Contamination control expertise
- Experience working near critical optical surfaces
- Project management experience
- Statistics: D.O.E., FMEA, FMECA, RCA
- PC skills: MS Office (Word, Excel, PowerPoint, Project, Math-Cad), Visio, Lotus Notes
- Strong analytical skills
- Ability to work independently as well as in functional team and project team environments
- Good verbal and written communication skills
- Comfortable making presentations and delivering training sessions
- Able to handle multiple tasks and changing priorities to meet challenging schedules
Please be aware that many of our positions require a security clearance, or the ability to obtain one. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.
For more Information or to Apply, please contact:
Space and Intelligence Systems
Ofc.: (585) 269-6006 pager: (585) 246-1942
Cell # (585) 764-2506
800 Lee Rd. P.O. Box 60488
Rochester, N.Y. 14606-0488
rm:2106 1/601 m/c 0488
NATIONAL SALES MANAGER
Male or Woman, 30- 55 (desirable)
Industrial, Electronics or Electrical Engineer (desirable)
Five years of previous experience as:
• Sales or Regional Sales Manager
• B2B Sales
• Electronics/ESD sales and its dealer network
• Knowledge of Electronics Industry
•Knowledge of General Management Processes
• Quarterly bonus depending on objectives achievement
For more information contact:
Phone: +52 01 33 30019900
Managing USA domestic sales.
Achieving financial objectives and opening markets within the electronics industry.
• Assisting the ESTATEC´S General Manager and Corporative CEO to develop the company´s introduction strategy to American market.
• Implementing that strategy with distributors.
• Planning the annual sales budget.
• Developing new customers according to the annual sales budget.
• Following up Top customers.
• Provide the attraction strategy for new customers
• Monitor the business strategy with Distributors Company.
• Solve customer complaints.
• Monitoring Billing and Collection
• Coordination of delivery and goods receipt.
• Supervision of warehouse operation and best practices
• Administration of the whole company resources.
• Resolve customer complaints about service and sales
• Solve products and service problems
• Ability to analyze
• Assertive communication
• Time management
• Customer-oriented service
• Complaints management
• MS Office
• Electronics and ESD
• Future sales forecast
• Market analysis
• Managing financial budgets