Job Description

B. Sampath Kumar

Research Scholar

Indian Institute of Science, Bangalore- 560012, Karnataka, India.

Email-id : boeila@iisc.ac.in

Mobile No.: +91-96321-34880

 

 ACADEMIC DETAILS                                                                                                 

 

Degree

University

Institute

Year

Post Graduate Specialization:

Electronic Systems Engineering

 

 

Ph. D.

IISc Bangalore

IISc Bangalore

Present

Post Graduate Specialization:

Microelectronics and VLSI

 

 

M. Tech

VNIT, Nagpur

VNIT, Nagpur

2013

UnderGraduate Specialization:

Electronics and Communication

 

 

B. Tech

JNTU, Hyderabad

JNTU, Hyderabad

2009

 

 KEY CONTRIBUTIONS                                                                                     

Sampath’s one of the key contributions is in unifying the physics of quasi saturation in power transistors [TED Jan.2018, Part I & II]. Until then, since 1986 the perception on peculiar conduction mechanism of power transistors remained ambiguous. Later, he has been actively involved and leading in development, enablement and integration of high voltage LDMOS device technology into deep sub-micron BiCMOS technolgy, which covers LDMOS devices with voltage range 7V-80V. His research also involves in exploring the high voltage feasibility for FinFET SoC applications, where he demonstrated the unique scope of device integration with superior device reliability [SISPAD 2017] [ISPSD 2018] [EOS/ESD 2018]. Besides this, a novel ESD protection element was co-invented for FinFET technology [EOS/ESD 2017] which was well received by the ESD community and encouraged by promoting it with an outstanding paper award for EOS/ESD 2017.

 

 LIST OF AWARDS                                                                                                 

  • Outstanding Paper Award, EOS/ESD Symposium, Sept
  • Honorable Mention Research Paper Award, VLSI Design Conference, Jan

 LIST OF PUBLICATIONS                                                                                     

  1. S. Kumar and M. Shrivastava, "Part I: On the unification of physics of quasi-saturation in LDMOS de- vices". IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 191-198, January 2018.
  1. S. Kumar and M. Shrivastava, "Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi-Saturation". IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 199-206, January 2018.
  1. Somayaji, B. S. Kumar, M. S. Bhat and M. Shrivastava, "Performance and Reliability Co-design for Super- junction Drain Extended MOS Devices". IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 199-206, January 2018.
  1. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, "Physics of Current Filamentation in ggN- MOS Devices Under ESD Condition Revisited". IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2981-2989, July 2018.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, "Performance and reliability insights of drain ex- tended FinFET devices for high voltage SoC applications". IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, 2018, pp. 72-75.
  1. S. Kumar, M. Paul, and M. Shrivastava, "On the design challenges of drain extended FinFETs for advance SoC integration". International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Ka- makura, Japan, 2017, pp. 189-192.

 

  1. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, "Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection". IEEE Transactions on Electron Devices, 2018.
  1. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, "Physics of Current Filamentation in ggN- MOS Revisited: Was Our Understanding Scientifically Complete?" 30th International Conference on VLSI De- sign and 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 391-394.
  1. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, "FinFET SCR: Design challenges and novel fin SCR approaches for on-chip ESD protection". 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.
  1. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, "Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability". IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.3- 1-3E.3-6.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, "Physical Insights into the ESD behavior of Drain Extended FinFETs". 40th EOS/ESD Symposium 2018, Reno, Nevada, USA.

N.K. Kranthi, B. S. Kumar, G. Boseli, Akram Salman, and M. Shrivastava, "Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability". IEEE International Reliability Physics Symposium (IRPS), Monterey, CA,(Accepted)

N.K. Kranthi, B. S. Kumar, G. Boseli, Akram Salman, and M. Shrivastava, "Performance and Reliability Co- Design of LDMOS-SCR for Self-Protected High Voltage Applications on-Chip". 31th International Symposium on Power Semiconductor Devices & ICs 2019, Shangai, China (Accepted).

  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. "Physical Insights, challenges & device design of high voltage drain extended FinFET transistors". (under submission) in IEEE Transactions on Electron Devices.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. "Electrostatic Discharge & Hot carrier reliability of High Voltage Drain extended FinFET transistors". (under submission) in IEEE Transactions on Electron Devices.
  1. Paul, B. S. Kumar, K. K. Nagothu, P. Singhal, H. Gossner and M. Shrivastava, "Fin Enabled Drain Ex- tended FinFET SCR for self-protected designs". (under submission) in IEEE Transactions on Electron Devices.
  1. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, "Hybrid Contact & Junction Engineering in Bulk FinFET Technology for improved ESD/Latch-Up Performance and HCI Reliability". (under submission) in IEEE Transactions on Electron Devices.

 LIST OF PATENTS                                                                                                 

  1. Paul, M. Shrivastava, B. S. Kumar, C. Russ and H. Gossner, "Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device". US Patent Pending, Application No: 15/883,306, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017).

 

 ENGINEERING SKILLS                                                                                     

Sentaurus Technology Computer Aided Design (TCAD) tools (Structure Editor, Device, Process, Mesh En- gines), Pspice, Cadence Virtuoso Layout Editor.

  • Scripting: Perl, Skill,

Electrical Characterization (HPPI Transmission Line Pulse (TLP) and Keithley 4200 and 2636B DC Charac- terization).

Course Undergone: Semiconductor Device Physics, Reliability of Nanoscale Transistors, Physics of Power Semiconductor Devices, Digital VLSI Design.

Mentoring: Training project assistants/interns/staffs in TCAD simulation environment, Skill Layout/GDS training, Process Simulations.

Technology development: High Voltage Design Integration: Process Split, Layout Splits, GDS Preparation, Design Rules.

 

 PROJECTS                                                                                     

High voltage semiconductor device design: Integration of high voltage device with Performance & Re- liability co-design for planar and non- planar (3D) CMOS technology (Research Project)

(Guide:Prof. Mayank Shrivastava , Dec’15 - till date)

Abstract: As part of research carrier, I began designing high voltage planar and 3D transistors computa- tionally for advance CMOS technology nodes. In planar CMOS technology front, I am leading a project on development & integration of high voltage LDMOS technology for semiconductor laboratory (SCL) which is a 0.18µm foundry, where my responsibilities were setting up a simulation framework emulat- ing the baseline SCL process, and introducing 5 new implant layers for annexing 7V, 20V, 40V & 80V nLDMOS transistors & 25V pLDMOS transistor. For this I had prepared 25 Mask Layer, 30mm2 test chip GDS, test chip documentation, test procedures & process recipes with process splits. At present, processing of wafer lot is scheduled. For 3D CMOS FinFET technology, we have analyzed the per- formance and high voltage feasibility with stacking FinFET transistors vs drain extended FinFETs.  Design challenges, performance limiters and design guidelines beyond 5V FinFET applications were examined. ESD & HCI reliability assessment and benchmarking with planar CMOS counterpart were done.

Implementation of fast fractal transform through FFT (M. Tech Project)

(Guide:Prof. S. B. Dhok, Prof. R. M. Patrikar , July’11 - July’13)

Abstract: In the masters program, Fast Fractorial Transform algorithms for image compression and de- compression were performed using discrete fast fourier transforms, where I have worked with FPGA kits with VHDL coding for faster implementation.

 

 VOLUNTARY ACTIVITIES                                                                                     

  • Organized India ESD Workshop (IEW) 2016, 2017 and 2019, at IISc Bangalore,
  • Organized IEEE CONNECCT 2018, at Bangalore,
  • IEEE, ESDA Essentials, Bangalore Chapter, held in Bangalore,

 REFERENCES                                                                                     

Dr. Mayank Shrivastava

Assistant Professor

Department of Electronic Systems Engineering Indian Institute of Science, Bangalore

Mail: mayank@iisc.ac.in

Phone: +91 80 2293 2732 (Work)

 

Dr. Harald Gossner Sr Principal Engineer Intel Corporation Neubiberg, Germany

Mail: harald.gossner@intel.com

Phone: +49 89 9988530 (Work)