Job Description

Milova Paul

Research Scholar

Indian Institute of Science, Bangalore- 560012, Karnataka, India.

Email-id : milova@iisc.ac.in

Mobile No.: +91-96321-35622

 

 ACADEMIC DETAILS                                                                                                 

 

Degree

University

Institute

Year

Post Graduate Specialization:

Electronic Systems Engineering

 

 

Ph. D.

IISc Bangalore

IISc Bangalore

Present

Post Graduate Specialization:

Microelectronics and VLSI

 

 

M. Tech

Delhi Technological University

DTU, New Delhi

2014

UnderGraduate Specialization:

Electronics and Communication

 

 

B. Tech

Maharishi Dayanand University

CITM, Faridabad

2011

 

 KEY CONTRIBUTIONS                                                                                     

Milova’s one of the key contributions is in designing of a novel Silicon Controlled Rectifier (SCR) as an ESD protection element for FinFET technology [EOS/ESD, 2017] [TED, 2018]. The robustness of the proposed design was shown to outperform the traditional SCR design approach as of planar CMOS know-how repository. Her work was appreciated by an Outstanding Research Paper Award by EOS/ESD symposium, USA in 2017. The key components of the novel device design had uncovered the critical understanding of ESD failure mechanisms and reliability pattern of FinFET devices [IRPS 2018]. Besides this, a unified physical trend in current filament with CMOS technology scaling was demonstrated [VLSID 2017] [TED, 2018]. Her research also involves in exploring the ESD and long-term reliability of advance CMOS technology devices.

 

 LIST OF AWARDS                                                                                                 

  • Outstanding Paper Award, EOS/ESD Symposium, Sept
  • Honorable Mention Research Paper Award, VLSI Design Conference, Jan

 LIST OF PUBLICATIONS                                                                                     

  1. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, "Physics of Current Filamentation in ggN- MOS Devices Under ESD Condition Revisited". IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2981-2989, July 2018.
  1. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, "Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection". IEEE Transactions on Electron Devices, 2018.
  1. Paul, C. Russ, B. S. Kumar, H. Gossner and M. Shrivastava, "Physics of Current Filamentation in ggN- MOS Revisited: Was Our Understanding Scientifically Complete?" 30th International Conference on VLSI De- sign and 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 391-394.
  1. Paul, B. S. Kumar, C. Russ, H. Gossner and M. Shrivastava, "FinFET SCR: Design challenges and novel fin SCR approaches for on-chip ESD protection". 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-6.
  1. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, "Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability". IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.3- 1-3E.3-6.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, "Performance and reliability insights of drain ex- tended FinFET devices for high voltage SoC applications". IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, 2018, pp. 72-75.

 

  1. S. Kumar, M. Paul, and M. Shrivastava, "On the design challenges of drain extended FinFETs for advance SoC integration". 22nd International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, 2017, pp. 189-192.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, "Physical Insights into the ESD behavior of Drain Extended FinFETs". 40th EOS/ESD Symposium 2018, Reno, Nevada, USA.
  1. Paul, B. S. Kumar, K. K. Nagothu, P. Singhal, H. Gossner and M. Shrivastava, "Fin Enabled Drain Ex- tended FinFET SCR for self-protected designs". (under submission) in IEEE Transactions on Electron Devices.
  1. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, "Hybrid Contact & Junction Engineering in Bulk FinFET Technology for improved ESD/Latch-Up Performance and HCI Reliability". (under submission) in IEEE Transactions on Electron Devices.
  1. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, "ESD and HCI Behavior of Stacked Bulk FinFETs".

(under submission) in IEEE Transactions on Electron Devices.

  1. Paul, C. Russ, H. Gossner and M. Shrivastava, "Insights into the turn-on behavior of mutli-fin arrange- ment in FinFET Technology under ESD conditions". (under submission) in IEEE Transactions on Electron De- vices.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. "Physical Insights, challenges & device design of high voltage drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.
  1. S. Kumar, M. Paul, H. Gossner and M. Shrivastava. "Electrostatic Discharge & Hot carrier reliability of High Voltage Drain extended FinFET transistors”. (under submission) in IEEE Transactions on Electron Devices.

 

 LIST OF PATENTS                                                                                                 

  1. Paul, M. Shrivastava, B. S. Kumar, C. Russ and H. Gossner, "Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device". US Patent Application No.: 15/883,306.(Indian Patent, Application No. 201741003771, Filed on 1st Feb. 2017).
  1. Shrivastava, M. Paul, C. Russ and H. Gossner, "Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks". US Patent Application No.: US20180226317A1, (Indian Patent, Application No. 201741003773, Filed on 1st Feb. 2017).
  1. Shrivastava, M. Paul, C. Russ and H. Gossner, "Low Trigger And Holding Voltage Silicon Controlled Rec- tifier (SCR) For Non-Planar Technologies". US Patent Application No.: US20180219007A1, (Indian Patent, Application No. 201741003772, Filed on 1st Feb. 2017).
  1. Shrivastava, M. Paul and H. Gossner, "FinFET SCR With SCR Implant Under Anode And Cathode Junctions". US Patent Application No.: US20180248025A1, (Indian Patent, Application No. 201741006746, Filed on 25th Feb. 2017).
  1. Shrivastava, M. Paul and H. Gossner, "Semiconductor devices and methods to enhance Electrostatic Dis- charge (ESD) robustness, latch-up, and hot carrier immunity". US Patent Application No.: US20180247929A1, (Indian Patent, Application No. 201741006745, Filed on 25th Feb. 2017).

 

PLATFORM PRESENTATION/TALKS                                                                                                 

  • IEEE VLSI Design Conference, Hyderabad, India,

Talk on "Physics of current filamentation in ggNMOS revisited: Was our understanding scientifically com- plete?", Indian ESD Workshop (IEW) 2017, IISc Bangalore, India.

  • IEEE EOS/ESD Symposium, Tucson, Arizona, USA,
  • IEEE International Reliability Physics Symposium (IRPS), Burlingame, USA,
  • Talk on "ESD Reliability of FinFET Technology", Indian ESD Workshop (IEW) 2019, IISc Bangalore,

 ENGINEERING SKILLS                                                                                     

Sentaurus Technology Computer Aided Design (TCAD) tools (Structure Editor, Device, Process, Mesh En- gines), Pspice, Cadence Virtuoso.

 

  • Scripting: Shell, Basic Python,

Electrical Characterization (HPPI Transmission Line Pulse (TLP) and Keithley 4200 and 2636B DC Charac- terization).

  • Technology development, Layout Skill

Course Undergone: Semiconductor Device Physics, Reliability of Nanoscale Transistors, Basics of Power Semiconductor Devices, Digital VLSI Design.

 

 PROJECTS                                                                                     

ESD/HCI Reliability of Non-planar Semiconductor Devices (Research Project)

(Guide:Prof. Mayank Shrivastava , Dec’15 - till date) Technical Environment: Sentaurus TCAD.

Abstract: Exploration of ESD and Latch-up Physics in emerging CMOS technology nodes in devices like

FinFETs, III-V FinFET, Gate All Around (GAA) or nanowire devices, in order to improve the power, performance and reliability aspects for consumer electronics applications.

Detection of ECG Signals using Wavelet based ECG Detector (M. Tech Project)

(Guide:Prof. Rajiv Kapoor , July’12 - July’14) Technical Environment: VHDL and MATLAB.

Abstract: This project aimed for detection of Electrocardiogram (ECG) signals using wavelet transform

(WT). A VLSI implementation of Classical Wavelet based ECG detector was performed, which was further extended to implement a novel multi-wavelet based ECG detection system.

 

 VOLUNTARY ACTIVITIES                                                                                     

  • IEEE, ESDA Essentials, Bangalore Chapter, held in Bangalore,
  • Organized India ESD Workshop (IEW) 2016, 2017 and 2019, IISc Bangalore,

 REFERENCES                                                                                     

Dr. Mayank Shrivastava

Assistant Professor

Department of Electronic Systems Engineering Indian Institute of Science, Bangalore

Mail: mayank@iisc.ac.in

Phone: +91 80 2293 2732 (Work)

 

Dr. Harald Gossner Sr Principal Engineer Intel Corporation Neubiberg, Germany

Mail: harald.gossner@intel.com

Phone: +49 89 9988530 (Work)

 

Dr. Christian Russ ESD Protection Expert Infineon Technologies Neubiberg, Germany

Mail: christiancornelius.russ@infineon.com

Phone: +49 89 23465555 (Work)