Job Description

Due to the geometry scaling and specific lithography features, implementing high-voltage (HV) I/O transistors may become a very challenging task in advanced gate-all-around vertically stacked horizontal nanowires (NWs) technologies. Using core transistors for HV I/O circuit design could be an alternative design solution without additional development cost of HV I/O transistors. In this I/O design exploration, the functional performance of I/O circuit will be the first challenge because of the complicated circuit architecture and transistor/circuit reliability concerns. The reliability concerns are not only related to FEOL device reliability, such as TDDB and HC degradation, but also related to Electrostatic discharge (ESD). The later one has become a major reliability concern in advanced CMOS technology and ESD robustness is always a key parameter in I/O circuit specifications. In fact, the technology roadmap has set the stage of the ESD challenges. There are two main technology options in CMOS scaling roadmap. The first one is the device architecture moving from FinFET to GAA NW. The second is the high mobility materials, such as SiGe, and Ge, integrated as the channel of the transistors in either FinFET or GAA NW. However, the technology options and complicated circuit architecture often result in significant impact on ESD robustness of the protection devices.

FEOL device reliability in static/quasi-static stress conditions has been investigated several advanced technologies [1-3]. However, in real circuit applications, the transient overshoot could bring severe overvoltage stresses which can significantly impact transistor performance and finally induce circuit performance degradation. This issue will be more pronounced in HV I/O circuit design with only core transistors. On the other hand, ESD reliability has been investigated in Si FinFET technology [4-9] and Si GAA NW [10] technology. It is strongly impacted by the process options and the specific device architecture [4-12]. Then, ESD characterizations of planar SiGe and FinFET SiGe technologies have been presented in our previous works [11, 12]. The SiGe quantum well channel plays an dominated role in ESD performance and the Si/SiGe heterostructure junction brings an isolation effect on carrier density and current distribution. In addition, the ESD results of the planar Ge technology and the FinFET Ge technology with the strain process option have been also shown in our previous works [13,14]. The non-destructive differential resistance lowering (DRL) was reported in Ge diodes because thermally induced carrier generation in Ge. The Ge/SiGe heterostructure junction not only induces the electrical isolation effect, but also bring the thermal isolation due to the thermal property difference in different materials. In a nutshell, the reliability challenges in I/O circuits of advanced CMOS technologies are directly from the interaction between specific process options, device architectures, the material properties, and even the circuit applications.


Job Responsibilities

In this PhD program, the main tasks will focus on ESD/FEOL reliability of I/O circuit applications in advanced FinFET and GAA NW technologies. Based on the past learning, we will start the exploration of the reliability influenced by specific circuit architectures, materials and the related process and device options, such as the nano-sheet architecture and the vertical GAA NW structure.

Job Qualifications

Required background: electrical engineering (solid-sate or analog IC design field), physics, material science.   Preferred: Si/compound semiconductor device physics, VLSI process/manufacturing/integration, TCAD process/device simulations, solid-state physics, layout/SPICE design environment

Type of work: 10% literature, 25% technology study, 40% experimental work, 25% TCAD simulation

Supervisor: Guido Groeseneken

Daily advisor: Shih-Hung Chen

Ref: [1] B. Kaczer, IEDM short course, 2016. [2] J. Franco, et al., IEDM Tech. Dig. 2017. [3] A. Chasin, et al., IEDM Tech. Dig. 2017. [4] S. Thijs, et al., EOS/ESD Symp., 2009, p. 76. [5] A. Griffoni, et al., EOS/ESD Symp., 2009, p. 59. [6] S. Thijs, et al., “EOS/ESD Symp., 2011, p. 27. [7] S.-H. Chen, et al., EOS/ESD Symp., 2013, p. 1. [8] D. Linten, et al., IRPS, 2013, p. 2B.5.1-8. [9] S.-H. Chen, et al., IEDM Tech. Dig. 2014, p. 514. [10] S.-H. Chen, et al., IEDM Tech. Dig. 2015, p. 362. [11] G. Hellings, et al., EOS/ESD symp., 2012, p. 1. [12] D. Linten, et al., EOS/ESD Symp., 2013, pp. 22-29. [13] R. Boschke, et al., EOS/ESD Symp., 2014. [14] R. Boschke, et al., EOS/ESD Symp., 2015.

The reference code for this PhD position is STS1712-26. Mention this reference code on your application form.


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