Job Description


Job ID: JR0229804

Job Category: Software Engineering
Work Mode: Hybrid
Experience Level: Experienced

The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US,TX,Austin;US,AZ,Phoenix;US,CA,Santa Clara

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here:

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Job Responsibilities

Responsibilities may included but are not limited to the following:

  • Development of ESD/LU rule decks based on Design Rule Manual (DRM) requirements
  • Creating reliability ESD and LU design rules specifications
  • Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification
  • Test-cases creation for debugging and validation
  • Define requirements for QA and related automation
  • Drive innovation and initiatives to enhance existing automation, tools and methodology
  • Identify and analyze problems, plans, tasks and solutions

Job Qualifications

Important behavior traits we look for:

  • Driving cross-functional and industry wide initiatives and task-forces
  • Ability to work in a dynamic and team oriented environment
  • Creative, independent and out of the box thinker with strong problem solving skills and analytical ability.
  • Attention to details, strong organization skills
  • Written and verbal communication skills to present complex issues with clarity to drive decisions

Minimum Qualification

MS/Ph.D. in Electrical Engineering or Computer Engineering with 3+ years of relevant experience in the following areas:

  • Calibre and ICV PERC tools
  • ESD/LU Pre-Si models (HBM and CDM), I/O design and methodologies
  • Debugging skills
  • Scripting languages for QA automation

Preferred Requirements :

  • Runsets, extraction and physical design domain
  • Knowledge of semiconductor device physics, process technology, and design rules