In this position, you will help ensure robustness of Intel’s leading edge technologies and products against damage from electrostatic discharge (ESD). Job duties include creation of ESD design rules, publication of ESD design documents, development of pre-silicon ESD design validation tools, and development of ESD protection devices and concepts. You will help process development and design teams to ensure the quality and reliability of Intel’s products and technologies.
Shift 1 (United States of America)
US, Oregon, Hillsboro
Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
The ESD Reliability R&D Engineer will be responsible for but not limited to:
- Analyze ESD data from test structures, test chips, and products to create design rules that aid in product design.
- Run ESD simulations on experimental and product circuits to ensure robustness and develop design guidance.
- Develop, document, and publish ESD design rules to aid both internal and foundry design teams.
- Serve as a consultant to design teams to ensure ESD-robust circuits.
- Plan and implement test structures on test chips.
- Develop ESD protection devices and concepts.
- Implement ESD design rule checking in industry-standard pre-silicon design validation tools such as PERC.
- Collaboration with cross functional teams to solve technical / design issues during technology development and product design.
- Work with partner groups including product design teams, Logic Technology Development (LTD), wafer Fab Manufacturing and Test (FSM), Assembly and Test Manufacturing (ATM), Intel Custom Foundry, and partners within Intel's Corporate Quality Network (CQN) focused on Product, Development, and Manufacturing Reliability.
The ideal candidate should exhibit the following behavioral traits:
- Verbal and written communication skills.
- Interpersonal skills.
You must possess the below minimum qualifications to be initially considered for this position. Qualifications listed as preferred or additional will be considered a plus factor for applicants.
- Candidate must possess at least one of the following:
- Ph.D. degree in Electrical Engineering, Material Science, Physics or related discipline with 2+ years of industrial experience designing on-chip ESD protection circuits.
- Master's degree in Electrical Engineering, Material Science, Physics or related discipline with 4+ years of industrial experience designing on-chip ESD protection circuits.
- Experience with transmission line pulse (TLP) measurement or data analysis.
- Experience with ESD device modeling and simulation.
- Knowledge of semiconductor device physics.
- Experience with on-chip ESD device characterization and development.
- Experience with semiconductor device fabrication, integration, and characterization.
- Experience in VLSI circuit design, including analog and digital.
- Experience programming with formal language (C,C++, C#, etc.) and scripting language (JSL, PERL, Python, SQL, TCL, VBScript, etc.)
- Experience planning and guiding the creation of test structure layout on test chips.