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• Workshop A1. Realistic Perspective on CDM Requirements From IC Design Challenges and Production Control Methods
  
  Moderator: Charvaka Duvvury, Texas Instruments

  CDM in recent years has taken on a more intense interest as the specification method to meet the ESD reliability for shipped IC products. While customers do require certain levels for product qualification there is no clear perspective on what is necessary and if these levels can always be met from circuit design constraints and other factors. This workshop raises many of these questions. How do customers decide what a safe CDM level is? If CDM failures are seen at production areas, is increasing the CDM protection levels on the chip really an effective solution? Do the sub-contractors understand the proper CDM control at the factory? Does the IC chip speed performance take precedence over the CDM reliability? Moving forward into the next generation of IC technologies, should we prepare the industry for a more realistic CDM road map? We invite the audience from both the customer side and the supplier side to participate in valuable discussions addressing these and many more questions on the CDM requirements.
  

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• Workshop A2. CBE: Board Level or Component Level?
  Moderator: Leo G. Henry, ESD/TLP Consultants, LLC

  This workshop continues the discussion of the Charged Board Event (CBE) phenomena. Several papers published over the past few years have shown that the physical damage from CBE can look like damage due to CDM or EOS, but the failure levels are much lower. Some authors have described this phenomenon as a board or a system level failure and attempted to differentiate it from the component level failure. However, a lot of questions remain. Does CBE require a separate model or is it just a subgroup of CDM ESD event? Is the CBE physical mechanism really the same as for CDM? How does one predict when the CBE will result in an ESD or in an EOS type failure? There is no established common procedure for the CBE, so please come to the workshop and share your experience, discoveries, ideas, opinions and procedures.
  

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• Workshop B1. What is the Impact of the ESD Requirement Changes on PCB Manufacturer and OEMs?
  Moderator: Reinhold Gaertner, Infineon Technologies; John T. Kinnear Jr., IBM
  

  The Industry Council on ESD target levels has published two White Papers (HBM and CDM) indicating that in the future the actual ESD target levels cannot be met anymore. What does this mean for the PCB manufacturer and the OEM? Are the OEMs afraid that the PCB manufacturer cannot handle these devices? Are the PCB manufacturers afraid that they deliver pre-damaged devices to the OEM? Is everybody afraid that he or she has to invest a lot of money for implementing advanced ESD protection? Do OEMs expect a significant change in ESD system level robustness? Or are HBM and CDM not the right models to address the ESD failures during production and/or in the field? These are some of the questions that will be discussed in this workshop between semiconductor supplier, PCB manufacturer and OEM.
  

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• Workshop B2. Controlling ESD in Modern Cleanroom Manufacturing Environments (Cleanroom ESD Issues / ESD Control Compatibility / Ionization Guidelines and Considerations)
  Moderator: Arnold Steinman, Electronics Workshop, Berkeley, CA

  The cleanroom is an integral part of the modern manufacturing environment. As devices become faster and feature sizes decrease, sensitivities to ESD and contamination increase. This workshop will focus on the use and compatibility of grounding methods, dissipative materials, and ionization in controlling ESD and contamination in modern cleanroom manufacturing environments. Experts from the semiconductor and disk drive industries will share their experiences and will answer questions related to current ESD and contamination control issues, such as selecting ESD and cleanroom safe materials, electrostatic attraction, the use of ionization and various other related topics. The workshop will offer those from other industries, such as electronics assembly, optics, and medical devices, the opportunity to discuss their needs and concerns as well.

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• Workshop B3. SPICE Simulation and Modeling for On-Chip ESD Protection Design
  Moderator: Michael Stockinger, Freescale Semiconductor, Inc.

  Being able to predict an integrated circuit’s behavior before implementing it on silicon reduces cycle time and development cost and increases the first-time success rate. Chip design without circuit simulation has therefore become unthinkable for most digital and analog applications. However, the available standard simulation tools usually have limited applicability for ESD with high current and voltage levels outside the normal operating regime of integrated devices. Designers often have to create extended ESD device models, for example in VerilogA, and match them to TLP data. This workshop is intended to increase the awareness of SPICE modeling for ESD and to serve as a discussion forum for several related topics. Can state-of-the-art ESD design be done without SPICE simulations? What is considered a “good” ESD model? Does CDM impose new requirements on transient model performance? What is the right balance between model accuracy and complexity? Have some ESD models become too difficult to handle? Which parts of an ESD protection network must be included in simulations and which ones can be neglected? Is there a need to include layout parasitic effects? After a brief introduction by the workshop panel, you will have the opportunity to engage in lively discussions about these topics.

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• Workshop B4. Issues and Future of the CDM Test
  Moderator: Horst A. Gieser, Fraunhofer IZM

  CDM is recognized as the main ESD threat in the electronics manufacturing environment, but there are a number of serious issues in today’s CDM test environment. Larger, thinner packages with higher capacitance are closing the CDM protection design window for the deep sub-micron technologies necessary for GHz bandwidth applications. Therefore, they need to be determined reliably and accurately. Today test methods with the inherent significant variability of air discharges are the basis for decisions on expensive and time consuming product redesigns. Even worse, the different competing standards from JEDEC, ESDA, and JEITA that allow wide, even overlapping tolerances (±20%), generate different stress currents for the same pre-charge voltage and thus different failure threshold voltages. Oscilloscopes with narrow bandwidths are hiding differences between testers and test heads. Without continuous monitoring and recording of the discharge currents for each pin, random low peak currents may conceal a weakness. Furthermore, stressing thousands of contact balls with three zaps per pin and per voltage level is occupying expensive test systems for days and delaying test results. Discussions about reducing the number of zaps from three to one and about the required robustness level have been started recently. The current motion to harmonize the CDM standards of JEDEC and the ESDA is a unique chance for developing alternative test methods that identify CDM sensitivities of integrated circuits faster and much more precise. This workshop will allow panelists and attendees to express concerns and describe a path to a better CDM test environment.
  

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• Workshop C1. Electrical Overstress (EOS): Many Failures and Few Solutions
  Moderator: Terry L. Welsher, Dangelmayer and Associates

  Electrical Overstress (EOS) remains, according to some sources, the most frequent diagnosis of returned integrated circuits. In this interactive workshop a panel of industry experts will help lead the discussion on several EOS topics. Why does EOS continue to be a large problem? Are the diagnoses generally correct or are causes such as Charge Board Events (CBE) becoming more prevalent? How do failure analysts distinguish among EOS, CBE, CDM and HBM failures? Why is there no EOS standard test? What are the best chip, board or system level protections against EOS? Workshop attendees will be encouraged to actively participate and share their own experience.
  

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• Workshop C2. ESD Control & Design for Extremely Sensitive Devices
  Moderator: Julian A. Montoya, Intel

  Class 0 devices require a proactive approach to enable ESD control. What are the design and control techniques required for manufacturability of all types of highly ESD sensitive devices? How can one make sure that a Class 0 device is safe? What safety margin can one afford to design into process, tools, and facilities? We will discuss considerations regarding product protection including, but not limited to semiconductor, HDD, and medical devices. Manufacturers constantly have to deal with a balance between cost and the ability to handle these extremely sensitive devices in a safe and cost effective manner. We will focus on techniques to protect against damage to extremely sensitive devices. Topics and issues concerning tool configuration, tool design practices, material selections, facility design practices, and test methods will be discussed in detail.

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• Workshop C3. Requirements and EDA Tools for ESD Design Verification
  Moderator: Vesselin Vassilev, Novorell Technologies

  This workshop will discuss the user requirements, the appropriate methodologies and the needed Electronic Design Automation (EDA) infrastructure to enable verification of the HBM, CDM and IEC stress reliability performance of Integrated Circuits and Systems. We will continue the open forum exchange between the ESD design community and the EDA vendors to identify the most critical ESD checks and the most suitable ESD EDA toolset, which will allow to substantially optimize the design ESD quality before manufacturing. A brief outline of the activities of the ESDA Workgroup on ESD EDA specifications will be given as well. The workshop panel will represent the visions on the topic of representatives from the EDA vendors, the IC design community and the ESD reliability professionals. The active participation of the audience is extremely important and highly encouraged. Please submit to the moderator any particular problem, question or topic you would like to be specially covered and analyzed in our discussion. We will use the worldwide, distributed, multi-experience based expert’s intelligence of all the workshop attendees to find the best answer!

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• Workshop C4. HMM - System Level ESD Pulses to Components: Application and Interpretation
  Moderator: Nathaniel Peachey, RF Micro Devices

  Customers have begun requesting system level test results from component and device manufacturers. Furthermore, some are looking to component manufacturers to supply the protection needed to survive a system level IEC 61000-4-2 test at 8 kV contact discharge. Since the system level test is not intended for components, there is no real standard whereby to apply this pulse to a device. The ESDA is completing the Human Metal Model (HMM) Standard Practice document to address this issue. This Standard Practice will address the application of the system level test to the device, but questions remain pertaining to the interpretation of these results. The system level test is expected to highlight system upset in an ESD event. How does that apply to a component or device? Assuming that the manufacturer is being required to supply protection, does an on-chip or an off-chip surface mount device make the most sense? The workshop will discuss these and other HMM topics.

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