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• Workshop A1. Human Metal Model Testing
  
  Moderator: Theo Smedes, NXP Semiconductor

  This workshop is a forum for attendees to discuss their experiences implementing the ESDA Standard Practice on Human Metal Model (HMM). Topics include correlation between device-level HMM performance and system level performance, measurement techniques, and experiences with system-level disturb failures—which may not be predicted by device-level testing.
  

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• Workshop A2. ESD Control for Class 0 Devices
  Moderator: Tim Iben, IBM

  Manufacturers are constantly challenged to find ways to handle ESD sensitive devices in a cost effective manner. This workshop is an opportunity to discuss tool configuration, tool design best-practices, material selection and factory design—in the context of both effectiveness for ESD control and cost.
  

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• Workshop A3. ESD Verification Checks Leveraging Existing Commercial EDA Tools
  Moderator: Robert Gauthier, IBM
  

  There is an industry-wide desire to involve EDA vendors in the creating new tools for ESD design verification. An interesting pre-cursor to new tool development is the use of existing tools in novel ways to solve new applications. This workshop is a forum for attendees to share ways that they have exploited existing EDA tools to solve ESD verification problems—perhaps giving EDA vendors new insights into how existing tools can be leveraged—and with what limitations.
  

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• Workshop B1. Sources of EOS Damage and Characterization Techniques for Determining EOS Robustness
  Moderator: Chai Gill, Freescale Semiconductor, Inc.

  This workshop will provide attendees an opportunity to
  discuss mechanisms that cause EOS damage. The workshop will focus on EOS mechanisms other than latch-up, exploring EOS mechanisms for which robustness requirements and testing standards are either limited in scope or non-existent (e.g., reverse power, over-voltage, and hot-plug). Attendees are encouraged to share techniques they have developed for characterizing EOS robustness.

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• Workshop B2. Board-Level Solutions to System-Level ESD Design
  Moderator: Harald Gossner, Infineon

  There has been a great deal of discussion in the ESD community regarding increasing requirements for full integration of system-level ESD protection on-chip. While this continues to be an important topic, there is also a need to discuss board-level solutions (components and techniques) to address the system level ESD problem. This workshop is an opportunity to discuss board-level protection strategies that do not require full integration of system-level ESD cells onto the IC. Co-design strategies where the board-level solution works in concert with the existing (non-system-level) on-chip protection will also be discussed.

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• Workshop B3. Common ESD Audit Issues
  Moderator: Ted Dangelmayer, Dangelmayer Associates, LLC

  ESD auditing is the driving force behind a solid ESD control program. This workshop is an opportunity to discuss common ESD audit findings and their proper solution with industry experts.
  

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• Workshop C1. Equipment Grounding Issues
  Moderator: Scott Ward

  This workshop will focus on ESD Control requirements for automated handling equipment. Common problems/solutions to equipment grounding in the factory will be discussed, including test methods for determining the effectiveness of a grounding strategy.
  

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• Workshop C2. Challenging Pin Applications in Analog Design
  Moderator: Gianluca Boselli, Texas Instruments, Inc.

  Product requirements often challenge state-of-the-art technologies and ESD design techniques. While there has been good discussion regarding high-speed digital and high frequency RF topics, there are numerous power analog, precision analog, high-voltage, and negative voltage requirements which present daily challenges to ESD Engineers across the industry. This workshop is an opportunity to share difficult applications and to discuss potential solutions.

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• Workshop C3. ESD Challenges Due to Package Scaling and Integration
  Moderator: Elyse Rosenbaum, University of Illinois at Urbana-Champaign

  Larger packages with higher pin counts and smaller pin pitch are increasingly complicating ESD testing. Further, increased integration of multiple ICs and even passive components into a single package is increasing ESD complexity—often pushing the need for ESD design verification up to the package integration level. ESD engineers are now being challenged to design ESD protection networks which cross IC boundaries—this workshop is a forum for discussing this evolving aspect of ESD design and testing.
  

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