1A.1 System-Event-Triggered Latch-up/ Lock-up in IC Chips: Test Issues and Chip Level Protection Design
IC devices that pass regular DC latch-up testing can still be triggered to latch-up and lock-up modes by system level events. This paper discusses IC level test environments for system events and IC level design efforts to enhance interface IC devices with latch-up/lock-up immunity to system events.

1A.2 A New Mechanism for Core Device Failure During CDM ESD Events
This paper identifies a mechanism where a CDM discharge applied to pins that are directly connected to long on-chip traces can couple inductively to adjacent long lines. The coupled energy bypasses ESD protection elements at the I/O buffers and causes failure in the non-I/O (core) circuit.

1A.3 ESD Damage due to HBM Stressing of Non-Connected Pins
ESD damage due to HBM stressing of non-connected pins is introduced. The failure mechanism is investigated and discussed. As a result, four different possible sources for a sparkover between non-connected and regular pins are introduced. Finally, possible countermeasures are discussed and recommendations are given to avoid similar failures.

1A.4 HBM Stress of No-Connect IC Pins and Subsequent Arc-over Events that Lead to Human-Metal-Discharge-Like Events into Unstressed Neighbor Pin
HBM ESD stress of no-connect pins causes unpredictable arc events. These arc events combine with HBM tester output capacitance to produce high magnitude currents into neighboring pins. Since there is no clear specification controlling these arc events, stress of no-connect pins provides no meaningful HBM product immunity data.

1B.1 Novel Technique to Reduce Latch-up Risk Due to ESD Protection Devices in Smart Power Technologies
N-well pockets connected to the cathode of ESD diodes may be source of parasitic electrons current in P-/P+ substrates. In this paper a methodology to reduce this latch-up risk is proposed. The electrical performance of this protection technique has been characterized and the results have been validated by device simulation.

1B.2 Turn-Off Characteristics of the CMOS Snapback ESD Protection Devices- New Insights and its Implications
Turn-off characteristics of various snapback devices are analyzed with experimental data for the first time. It is demonstrated that the residual voltage after turn-off depends on the type, architecture and layout of the ESD device. This enables an additional level of design freedom and flexibility for high-voltage-process ESD protection.

1B.3 Characterization and Modeling of Three CMOS Diode Structures in the CDM to HBM Timeframe
We present advanced TLP measurement techniques down to 1.2 ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe. Further, we compare diode area efficiency in a full ESD protection network.

2A.1 ESD Protection Considerations in Advanced High-Voltage Technologies for Automotive
This paper discusses the challenges of automotive ESD protection in a reliability driven industry. Various ESD/EMC specifications are compared, which impact the development of automotive technologies. Different ESD device types are discussed concerning fabrication and operation stability. The product examples demonstrate the challenge of protecting analog high voltage circuits.

2A.2 Dual-Direction Isolated NMOS-SCR Device for System Level ESD Protection
A novel dual-direction device is suggested for system level ESD protection. The device combines both a deep NWELL Isolated Snapback NMOS and a lateral SCR structures using the shared regions approach. ESD pulse operation of the device has been studied for a 0.35 µm CMOS process.

2A.3 Area-Efficient Reduced and No-Snapback PNP-based ESD Protection in Advanced Smart Power Technology
A new approach, based on reduced, no-snapback components, was studied to satisfy high-voltage ESD specifications. An accurate physical analysis of the ESD mechanisms led to a quantification of the attainable performance. Design rules are drawn to take full advantage of self-biased PNP for optimum efficient protections.

2A.4 ESD Protection for the High-Voltage CMOS Technologies
Two process and application portable ESD protections for the High Voltage CMOS technology are presented. First a stack of Low-Voltage transistors offering both a scalable triggering and holding voltage. Secondly, a RC-triggered HV-MOSFET with a compact-area triggering stage developed with electrical simulation using the usual design kit.

2A.5 Operation Analysis and Implementation of CMOS Compatible Vertical Bipolar ESD Protection Devices for Automotive Applications
In analysis of CMOS compatible vertical bipolar ESD protection, resistor avalanche breakdown in collector region was identified as a dominant factor in ESD failure mechanism. A new collector structure alleviating this mechanism was implemented which achieved excellent ESD performance and latch-up immunity for automotive application.

2B.2 ESD Induced Instability of Pinned Layer in GMR Head
ESD robustness of pinned layer was studied for GMR heads via high field transfer curve with damaged pinned layer using quasi-static tester (QST). Degradation of the pinned layer was induced by nano-pulse ESD and detected/characterized via high field QST.

2B.3 Study on EMI Phenomena for GMR/TMR Head
There is great concern over whether EMI may damage, and how it may damage, GMR and TMR heads. This paper applies conventional EMI evaluation techniques to comprehend the characteristics of EMI damage of GMR/TMR heads.

2B.4 Breakdown Evaluation of Ultrathin Barrier Magnetic Tunnel Junctions with V-Ramp Testing
Ultrathin alumina barrier magnetic tunnel junctions (MTJs) were tested using ramp voltage with different ramp speeds at room temperature. Both intrinsic and extrinsic distributions of breakdown voltage were found and correlated to models.

2B.5 A Resistive Ferrite Substrate for the GMR Head in Helical-scan Tape Systems
In order to use GMR heads in helical-scan tape systems, the risk of electrostatic discharge must be reduced. One method of doing this is to use dissipative substrates, and this paper finds that one suitable candidate is resistive ferrites.

2B.6 Effect of Electrostatic Discharge on Tunneling Magnetoresistive Recording Head
Tunneling magnetoresistive (TMR) heads offer adequate signal for higher recording densities, but have a different structure from conventional GMR heads. Several behaviors of ESD for alumina barrier TMR devices are presented here.

2B.7 Thermal Characteristics of PtMn GMR Sensor Subjected to Square Wave EOS Pulses
GMR tape heads were subjected to square wave EOS pulses of duration 50ns to 100ms. Thermal, resistance, and magnetic characteristics were compared to theoretical values using thermal diffusion and interdiffusion/electromigration model predictions.

2B.8 A New Electrical Overstress (EOS) Test for Magnetic Recording Heads
Grounding, used for ESD prevention, can itself become a method of introducing damaging signals to ESD/EOS sensitive components. To deal with this, SPICE models are developed and evaluated, and a consistent test method proposed.

3A.2 Cable Discharges into Communication Interfaces
Cable discharge events (CDE) have been recorded for several cables in different configurations. Current amplitudes of CDEs are a risk for electronic interfaces if a cable can discharge directly into a signal pin. CDE can be modeled by square pulses, thus, TLP is a good approach for characterizing interface pins and protection elements.

3A.3 Radiated ESD Noise of 5GHz-band from Walkers
Radiated ESD noise from walkers was observed in 5GHz-band in order to study the effects on the quality degradation of radio communications. It was clarified that the radiated ESD noise is originated by “Conducted ESD” and “Induced ESD”, when people walks in the condition that they wear some metal objects.

3A.4 EMI Power Measurements of ESD Radiated Fields
ESD radiated fields are measured using an “EMI power meter” developed by the author. This instrument measures amplitude (max -10dbm) and band-width (max 500MHz) of a single shot impulsive noise, such as ESD. One of the measurement results shows that metal-metal ESD has a powerful EMI effect to high-speed digital electronics.

4A.2 Concept for Bulk Coupling in SOI MOS Transistors to Improve Multi-Finger Triggering
Multi-finger SOI MOSFETS exhibit low failure current related to the thin Si-film and the isolation of the bulk regions, causing non-uniform bipolar snapback. This paper proposes a layout concept to improve uniform triggering. ESD performance around 3mA/um2 is achieved for minimum dimension, fully silicided 90nm devices in 90nm SOI technology.

4A.3 Design and Characterization of a Multi-RC-Triggered MOSFET-based Power Clamp for On-Chip ESD Protection
We present a novel three-stage RC-triggered MOSFET power clamp with up to 70% trigger circuit area reduction and improved transient HBM/MM/CDM ESD clamping performance. TLP and HBM hardware characterization data from a 90nm CMOS technology show >5A failure current and >3kV HBM robustness with a designed MOSFET width of 4000µm.

4A.4 Comprehensive ESD Protection for Flip-Chip Products in a Dual Gate Oxide 65nm CMOS Technology
We introduce and demonstrate on product, un-terminated distributed and boosted active MOSFET rail clamp networks for use in flip-chip products. A key challenge was to fit all required ESD elements for an OVDD segment wholly into the I/O cells of that segment, without need for power/ground or spacer cells.

4A.5 An Active ESD Protection Technique for the Power Domain Boundary in a Deep Submicron IC
A novel ESD protection technique which prevents failure of boundary circuits in an IC with separated power pins from ESD stresses by controlling the boundary circuits is proposed. Measurement results of test chips in a 90nm CMOS show that this technique improves the equivalent HBM level from 1.9kV to 6.2kV.

4A.6 ESD Protection Design for Mixed-Power Domains in 90nm CMOS with New Efficient Power Clamp and GND Current Trigger (GCT) Technique
An efficient power clamp and GND current trigger (GCT) technique are proposed for mixed-power domains. By using these techniques, we have achieved excellent ESD performance (MM: 500V) in a 90nm CMOS technology. The GCT technique is effective for a second clamp or an SCR as cross clamp for mixed-power domains.

4A.7 Tunable Bipolar Transistor for ESD Protection of HV CMOS Applications
A new ESD device for high voltage CMOS applications is presented exemplarily for a 90nm CMOS technology. The high-current characteristic of this lateral bipolar device can be adjusted in a wide range by implant dose and layout trimming. This enables protection of pads operating at voltages exceeding maximum MOS specification.

4A.8 High Voltage ESD Protection Strategies for USB and PCI Applications for 180nm/130nm/90nm CMOS Technologies
A substrate pump based cascoded MOSFET structure is presented for protecting high voltage power supply for deep submicron CMOS supporting fail-safe and 5V tolerant operation, e.g. for USB and PCI high speed interfaces. Data is presented for 180 nm, 130 nm and 90 nm processes. Latchup immunity and >2kV HBM performance are demonstrated.

4B.2 Development of Ion Balance Sensor by using MOSFET
A new ion balance sensor was developed to control ion generation of an air ionizer. The sensor, in spite of its very simple structure, can detect the ion balance instantly with enough sensitivity, with smaller response time, and higher spatial resolution compared to a charged plate monitor.

4B.3 Trends in External Ionizer Monitoring and Control
Many corona ionizers accept feedback from external sensors to monitor and maintain ionizer performance. This paper discusses sources of ion balance variability, and it introduces external feedback sensors and mechanisms that can be used to adjust the operating parameters of the ionizer to control the quality of the ion field.

4B.4 Ionization Applications and Pitfalls for Charge Neutralization in Substrate Handling
Charge acquired on a bottom substrate surface with ionizers over the top surface could result in charges of opposite polarities being deposited on the top and bottom surfaces. This could result in a discharge between the conducting structures of the substrate. A consequence of this “bipolar charge” is reduced breakdown voltage and is discussed in detail.

4B.5 Is CO2 Bubbling (Carbonization) a Requirement at Semiconductor Wafer Sawing Process
To avoid contamination of wafers, ultra-clean, de-ionized (DI) water is used in the wafer sawing process as a cleaning media and lubricant. There are claims that the high resistivity of DI water creates static charges that cause damaging ESD voltages. Investigations are conducted, and results and conclusions are presented.

4B.6 Solution of Destructive Separation Charge Generation
Charge generated when a glass substrate or wafer is lifted from a holding stage causes transfer problems or spark discharges. Ionization alone cannot prevent charge generation or its hazards. Several surface treatments to prevent separation charge are compared, including advanced charge-prevention fluoropolymers.

4B.7 Paper Withdrawn

4B.8 Voltage Dependence of Spark Resistance at Low Voltage ESD in Air and Reed Switch
This paper proposes a new and simple method to estimate low voltage spark resistance through an air gap, dry reed switch, and mercury switch using a CT-6 current probe. The spark resistance is estimated by comparing the measured waveforms against calculated current waveforms.

5A.2 Ultra-thin Gate Oxide Reliability in the ESD Time Domain
TDDB for ultra-thin gate oxides follows a power law model from “DC” down to the ESD regime. It is shown that the gate oxide breakdown predictions towards the CDM regime previously used are too optimistic. The cumulative effect of dielectric degradation should be considered in the ESD design window.

5A.3 Transmission Line Pulse (TLP) Testing of on Radio Frequency (RF) Micro-machined Micro-electromechanical-(MEMS) Switches
Ohmic and Capacitive RF-MEMS switches have been fully characterized regarding their robustness to ESD phenomena. Furthermore, an extension to classical TLP plot analysis is presented and it is demonstrated that this technique is necessary to correctly investigate the TLP response of capacitive RF-MEMS switches.

5B.2 Using Coupled Lines to Produce Highly Efficient Square Pulses for VF-TLP
A directional coupler can produce an impedance-matched square pulse if a voltage step with an overshoot of the correct magnitude and timing is its input. An augmented transmission line is used to produce this overshoot. Efficient generation of square pulses with a high return loss is demonstrated.

5B.3 A Frequency-Domain VFTLP Pulse Characterization Methodology and its Application to CDM ESD Modeling
The risetime and pulse width of a VFTLP pulse are extracted from frequency-domain measurements performed using a spectrum analyzer. A trapezoidal waveform in the time domain is assumed for this analysis. The risetime and pulsewidth of the VFTLP system are found to be 25 ps and 300 ps, respectively.

5B.4 Pre Pulse Voltage in the Human Body Model
The pre-pulse voltage present on low-leakage HBM stress points prior to the HBM current pulse is found to be a function of device geometry, capacitance, resistive loading and velocity of approach, both in simulated and real-world HBM events.

5B.5 Methods to Remove Anomalies from Human Body Model Pulse Generators
Small anomalies found in pulses produced by HBM testers may have adverse effects on HBM failure levels. A review of these anomalies and their causes is presented. A new HBM pulse generation system that eliminates or minimizes these anomalies is proposed.

5B.6 Different CDM ESD Simulators Provide Different Failure Thresholds from the Same Device Even Though All the Simulators Meet the CDM Standard Specifications
CDM standards allow or require the use of limited bandwidth oscilloscopes that do not capture the true CDM discharge waveform. The significantly different pulses produced by different testers may yield different failure thresholds, yet the testers all meet the standards. Standards require updating for repeatable failure thresholds to be obtained.

5B.7 HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Groups
HBM stressing of high-pin count components with multiple power/ground pins on automated HBM testers result in waveforms that differ significantly from the standard two-pin short circuit waveforms defined in HBM STM5.1. This is caused by floating parallel power or ground pins that create a parasitic AC current path to ground.