Monday, May 12
Registration & Check-In
1:00-10:00 p.m. Registration - Check-in
Seminars
1:30-2:50 p.m. Seminar #1
Package Influence on ESD Robustness
Charvaka Duvvury, Texas Instruments
2:50-3:00 p.m. BREAK
3:00-4:20 p.m. Seminar #2
Advanced Failure Analysis with
respect to ESD Failures
Philippe Perdu, CNES
4:20-4:50 p.m. BREAK
4:50-6:10 p.m. Seminar #3
Pulsed Characterization in the
ESD Domain
Evan Grund, Grund Technical Solutions LLC
6:10-6:20 p.m. BREAK
6:20-7:40 p.m. Seminar #4
ESD simulation and verification of complex
HV analog blocks in Smart Power IC’s
Antonio Andreini, STMicroelectronics
Lorenzo Cerati, STMicroelectronics
8:00 p.m. DINNER
Tuesday, May 13
7:00 a.m. BREAKFAST
8:00 a.m. Welcome & Announcements
Marise Bafleur, LAAS, Finance,
Registration & Arrangements
8:05 a.m. Introductions
Harald Gossner, Infineon,
Publications & Communications
8:10 a.m. Technical Program Overview
Horst Gieser, Fraunhofer IZM, Technical Program Chair
Keynote Address
8:20-9:15 a.m. Invited Keynote
Challenges and solutions for ESD protection
in advanced logic and RF CMOS
Guido Groeseneken, imec, KU Leuven
9:15 a.m. Break
Technical Presentations
Session A - Advanced CMOS - I
9:35 a.m. Opening
9:40-9:55 a.m. Presentation A.1
Drain Junction Versus Gate Oxide Breakdown Voltage in 65nm -Guido Notermans, Theo Smedes, Željko Mrčarica, Peter de Jong, Ralph Stephan, Hans van Zwol, Dejan Maksimovic, NXP Semiconductors
9:55-10:10 a.m. Presentation A.2
ESD Sensitivity of 65-nm Fully Depleted SOI MOSFETs With Different Strain-Inducing Techniques - A.Griffoni, A.Tazzoli, S.Gerardin, G.Meneghesso, DEI, Universitá di Padova, E.Simoen, C.Claeys, IMEC Belgium
10:10-10:25 a.m. Presentation A.3
Local CDM Protection for Input Drivers and Core Transistors Having Isolated Wells in Advanced CMOS Technologies - Bart Sorgeloos, Geert Wybo, Johan Van der Borght, Michaël Roseeuw, Sarnoff Europe
10:25-10:50 a.m. Discussion
10:50-11:05 a.m. Presentation A.4
ESD Protection Using Grounded Gate, Gate Non-Silicided (GG-GNS) ESD NFETs in a 45nm SOI Technology - S. Mitra, R. Gauthier, M. Abou-Khalil, J. Li, C. S. Putnam, R. Halbach, C. Seguin, IBM Microelectronics Semiconductor Research and Development Center
11:05-11:20a.m. Presentation A.5
Effect of Gate-Bias on ESD Performance of Silicide-Blocked Stacked NMOSFETs in a 45nm Bulk CMOS Technology - K. Chatty, M. J. Abou-Khali, J. Li, R. Gauthier, IBM Systems and Technology Group
11:20-11:35 a.m. Presentation A.6
Design Methodology for FinFET GG-NMOS ESD Protection Devices - S.Thijs, G.Groeseneken, IMEC vzw and Katholieke University, C.Russ, Infineon Technologies, D.Trémouilles, LAAS/CRNS, D.Linten, M.Scholz, M.Jurczak, N.Collaert. R.Rooyackers, C.Duvvury, Texas Instruments Inc.
11:35 a.m.-12:10 p.m. Discussion & Conclusion
12:10-1:00 p.m. LUNCH
Session B - Device Testing HBM/CDM
1:10 p.m. Opening
1:15-1:30 p.m. Presentation B.1
ESD Test Reduction Methodology for Complex Devices -Dejan Maksimovic, Guido Notermans, NXP Semiconductors, Fabrice Blanc, ARM Grenoble Design Centre
1:30-1:45 p.m. Presentation B.2
CDM Testing with Single Versus Multiple Pulses and its Implication on Realistic Product Qualification -Agha Jahanzeb, Charvaka Duvvury, Peter Koeppen, Joe Schichl, James McGee, Steve Marum, Texas Instruments
1:45-2:00 p.m. Presentation B.3
Investigations on the Correlation of Capacitive Coupled TLP at Package Level with the CDM - H. Wolf, H. Gieser, Fraunhofer IZM; A. Jahanzeb, C. Duvvury, Texas Instruments
2:00-2:30 p.m. Discussion & Conclusion
2:30 p.m. BREAK
Session C - System Level Testing
3:00 p.m. Opening
3:05-3:20 p.m. Presentation C.1
System Level CBM Stress Method for Risk Assessment -Pasi Tamminen, NOKIA Corporation, Toni Viheriäkoski, Nokia Siemens Networks
3:20-3:35 p.m. Presentation C.2
Evaluating IC Components Utilizing IEC-61000-4-2 -Donna Robinson-Hahn, Jay Chapin, Bruce Lyons, Fairchild Semiconductor
3:35-3:50 p.m. Presentation C.3
Investigation on Discharge Current Waveforms in Board-Level CDM ESD Events With Different Board Sizes - Yuan-Wen Hsiao, Ming-Dou Ker, National Chiao-Tung University
3:50-4:05 p.m. Presentation C.4
Delivering the IEC 61000-4-2 Current Pulse Through Transmission Lines at 100 Ohm and 330 Ohm System Impedances - E. Grund, Grund Technical Solutions, K. Muhonen, Penn State Erie; N. Peachey, RFMD
4:05-4:35 p.m. Discussion & Conclusion
4:35-5:00 p.m. break
Invited Presentation with Q&A
5:00-6:00 p.m. Industry Council ESD Target Levels
Charvaka Duvvury, Texas Instruments
Discussion Groups
6:00-7:30 p.m. DG 1: System Level
DG 2: ESD Wafer/Product Failure Criteria
7:30-8 :30 p.m. Dinner
Special Interest Group
8:30-9:30 p.m. SIG 1: CDM/CBM- Is it time to develop
a CBM document?
Wednesday, May 14
7:00-8:00 a.m. BREAKFAST
8:00-8:30 a.m. Summary of SIG and Discussion Groups
Technical Presentations
Session D -Simulation & Characterization
8:30 a.m. Opening
8:35-8:50 a.m. Presentation D.1
Characterization and Modeling of SCR and NMOS Snapback from DC Down to CDM Time Domain -Pascal Fonteneau, Jean-Robert Manouvrier, Charles-Alexandre Legrand, Helene Beckrich, Corinne Richier, Ghislain Troussier, Fanny Landré, Christopher Entringer, Nicolas Blisson, ST Microelectronics
8:50-9:05 a.m. Presentation D.2
Transit Time Extraction Method for ESD Protection Diodes Model -Jean-Robert Manouvrier, Pascal Fonteneau, Charles-Alexandre Legrand, Corinne Richier, ST Microelectronics, Pascal Nouet, Florence Azais, LIRMM
9:05-9:20 a.m. Presentation D.3
Alternative GGNMOS Triggered SCR ESD Protection Structure in CMOS Technology for the Manufacture of High-Density Integration Circuits - Fabio Alessio Marino, Gaudenzio Meneghesso, DEI, University of Padova
9:20-9:50 a.m. Discussion & Conclusion
9:50 a.m. Break
Session E - EDA Methods and Tools
10:00 a.m. Opening
10:05-10:20 a.m. Presentation E.1
Overview of ESD Electronic Automation Check Requirements -M. G. Khazhinsky, Freescale Semiconductor, Inc.; V. Vassilev, Texas Instruments; H. Gossner, Infineon Technologies; R. Consiglio, Impulse Semiconductor, Inc.; E. Franell, Infineon Technologies and TU Munich; K. Hsueh, UMC; N. Trivedi, NXP Semiconductors
10:20-10:35 a.m. Presentation E.2
CDM Verification by Distributed Current Sources and DC Simulation -Enrico Franell, Doris Schmitt-Landsiedel, TU Munich, Harald Gossner, Infineon Technologies
10:35-11:00 a.m. Discussion, Conclusion and Poster highlights
11:00 a.m. Group Picture
Special Interest Groups
11:15 a.m.-12:30 p.m. SIG 2: TLP correlation/mis-correlation to the
ESD Models
SIG 3: EDA Tools & Flow for ESD Verification
12:30 p.m. Lunch
1:00-6:00 p.m. Free time
6:00-7:00 p.m. Poster Session and Mixer
7:00-8:30 p.m. DINNER
Discussion Groups
8:30-9:30 p.m. DG 3: ESD Design Window Scaling
DG 4: ESD Smart Power/High Voltage
Thursday, May 15
7:30-8:30 a.m. BREAKFAST
Technical Presentations
Session F - MEMS and Smart Power
8:30 a.m. Opening
8:35-8:50 a.m. Presentation F.1
ESD Issues in MEMS: A Case Study in Micromirrors -Sandeep Sangameswaran, Steven Thijs, Chris Van Hoof, Guido Groeseneken, Ingrid De Wolf,IMEC vzw and KU Leuven, Jeroen De Coster, Dimitri Linten, Mirko Scholz, Luc Haspeslagh, Ann Witvrouw, IMEC vzw
8:50-9:05 a.m. Presentation F.2
190V LIGBT Implementation as ESD Protection for 0.35µm Smart Power Technology realized on SOI Substrate - Eleonora Gevinti, Lorenzo Cerati, Marco Sambi, Mariano Dissegna, Luca Cecchetto, Antonio Andreini, ST Microelectronics
9:05-9:20 a.m. Presentation F.3
Analysis of High Voltage ESD Protection Devices Under HBM ESD Stress - D.Linten, M.Scholz, P.Jansen, IMEC vzw, V.Vashchenko, D.Lafonteese, P.Hopper, National Semiconductor, S.Thijs, G.Groeseneken, Katholieke University Leuven, M.Sawada, T.Hasebe, HANWA Electronics
9:20-9:35 a.m. Presentation F.4
ESD Investigation on Very High Density Embedded Capacitors Frederic Barbier, Sebastien Jacqueline, NXP Semiconductors
9:35-10:00 a.m. Discussion & Conclusion
10:00-10:45 a.m. Break (check out of room)
10:45-11:15 a.m. Discussion Group/Sig Summary
11:50 a.m. Closing
12:00 p.m. Lunch |
