| Latchup continues to be of interest today
in advanced CMOS, mixed signal (MS) CMOS, RF CMOS, BiCMOS, and BiCMOS
silicon germanium. The latchup tutorial will provide a discussion
on device-level latchup physics, latchup metrics and design criteria,
latchup test structures, test methods, latchup measurement techniques,
device-level CAD simulation, and new latchup issues. Both internal
and external latchup phenomenon, as well as DC and transient latchup,
will be addressed. Latchup structures, guard ring physics, and characterization
will be discussed in depth. The tutorial will provide examples of
discussion on latchup device level simulation using latchup scaling
issues as examples. Latchup process solutions, such as heavily doped
buried layers (HDBL) and triple wells will be shown. The tutorial
will briefly discuss latchup standards. The tutorial will end with
a discussion on the state-of-the-art latchup issues and characterization
techniques and tools.
|
