Over the past 10 years, there has been a gradual revolution in the world of ESD design for advanced technology CMOS ICs. On-chip ESD networks built with non-snapback ESD devices and circuits, including simple forward biased diodes and active MOSFET rail clamp circuits have increasingly replaced once prevalent networks built with snapback ESD devices, including avalanche triggered lateral bipolar transistors and SCRs. Non-snapback devices enjoy several advantages in process portability, scalability, layout area and ease of compact modeling for circuit simulations in SPICE. In this tutorial we will explore in turn each of the key elements in typical active ESD networks including diodes, power busses, and active clamp devices with trigger circuits. We will also review approaches for ESD-hardening of the fragile output driver transistors. Next, a step-by-step methodology for SPICE-based ESD network design and optimization will be introduced. Finally, the flexibility of active ESD networks will be demonstrated in a wide range of IC application examples.