WWW.ESDA.ORG

Program

ESD Certified Professional-Device/Design Engineer

Course Length

Half-day course

Description

This tutorial addresses the basics of HBM, CDM, MM, and TLP ESD stress testing of the ESD protection structures of ICs. The differences between these models is emphasized and used to show how the different circuit parasitics affect the waveforms from each model-type simulator. The importance of doing ESD testing as an integral part of a high quality component development and qualification efforts is stressed. This tutorial covers constant impedance and constant current TLP testing and the TLP I-V characteristic plots, including the snap-back trigger voltages and currents. The evolution of the leakage current as it relates to the failure point and comparisons and correlations between HBM and TLP testing are emphasized. Standards issues and test procedures, including some comparison between the ESDA and JEDEC standards will be discussed.