This tutorial addresses important issues in the design of IC protection
circuits built with advanced deep sub-micron CMOS technologies, including
silicon-on-insulator (SOI) and high voltage MOSFETs. The tutorial will
present fundamental aspects of ESD protection design such as basic NMOS
and SCR concepts, as well as gate-biased and substrate driven NMOS protection
concepts. Protection design methods to meet the human body model (HBM),
machine model (MM), and charged device model (CDM) will be presented.
Other topics to be covered include BiCMOS protection circuits, mixed
voltage protection, and compatibility to latch-up. Specific design examples
will be presented to assist in understanding the methods for design
synthesis. This tutorial is useful for design, device, process, product,
failure analysis, and reliability engineers and will assist those attending
other design related tutorials. Attendees should have a minimum knowledge
of MOS device operation in integrated circuits.
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