| These seminars are dedicated to the basic concept of IEW to provide first
hand information presented by highly distinguished experts. Be invited to
take benefit from lectures which span from fundamental considerations to the
presentation of most advanced techniques applied for ESD characterization,
simulation and protection concepts.
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'Package Influence on ESD Robustness'
by Charvaka Duvvury
This seminar reviews the technology and circuit trends that are making ESD
design a difficult task, followed by identification of the specific package
development issues that further restrict the ESD design. The focus will be
on the IC package historic roadmap and the general impact on ESD for both
HBM and CDM. These issues will be tied together in discussing an ESD
roadmap that comprehends realistic ESD specification goals for the near
future.
Charvaka Duvvury is a Texas Instruments Fellow working in the Advanced CMOS
Technology Design Interface Organization. He has been involved in the ESD
development for nanometer submicron CMOS technologies and is a company wide
consultant on ESD and Latchup related issues for many different product
groups. Charvaka received his Ph.D. in Engineering Science from the
University of Toledo. He has published over 120 papers in technical journals
and conferences and holds more than 60 patents. Charvaka has been very
active in the ESD Symposium where he was the General Chairman both in 1994
and in 2005. He is a Director of the ESD Association Board. He is also a
Fellow of the IEEE. Charvaka jointly initiated the Industry Council on ESD
Target Levels, and now co-chairs this Council in establishing safe and
realistic component ESD target levels.
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'ESD simulation and verification of complex HV analog blocks in Smart Power
IC's' by Antonio Andreini and Lorenzo Cerati
Smart Power technologies are characterized by a wide variety of applications
spanning on a large voltage range (up to almost 1000 V). The key element is
a strong technology customization to increase voltage and component offer.
This results in a very complex ESD strategy, which must be carefully tuned
to the single application needs. Predictable ESD robustness may greatly
reduce time-to-market and therefore the development of proper ESD simulation
tools is a must to ensure the success of new technology platforms. This
seminar deals with the different simulation approaches which could be
effectively used to virtually assess the ESD robustness of medium-complexity
Smart Power IC's together with the protection elements. TCAD simulations
(process & device) can be successfully implemented to study simple ESD
protections. Simulations pre-requisites together with some case studies will
be presented in the first part of the seminar, highlighting the capabilities
and limits of this approach. The second part will be focused on the circuit
simulation approach: the need for different solutions covering HBM & CDM
stresses will be highlighted. The simulation pre-requisites (external
elements, dedicated Safe Operating Area limits, compact models extraction
and validation) will be closely analysed. Finally, HBM and CDM circuit
simulation examples of complex and high voltage analog blocks will be
presented.
Antonio Andreini graduated in Physics at the University of Milan in 1983.
Since 1983 he has been working in STMicroelectronics starting his activities
from the development of discrete Power MOS components. He then moved to the
development of mixed processes dedicated to the design of Power ICs,
contributing to begin the development of the BCD (Bipolar CMOS DMOS) process
family: he has worked on different generations of this process family,
covering mainly the high voltage field, both junction and dielectric
isolated.
Currently he is managing the activities of the ESD protection design and
reliability characterization for Smart Power and High Voltage technology
platforms, together with specific developments of common use in those
technologies.
He published several technical papers and got many international patents in
all the mentioned technical fields.
He has been involved as STMicroelectronics responsible in international
funded R&D projects in the ESD field, labeled by the MEDEA consortium.
Lorenzo Cerati graduated in telecommunication engineering at the
"Politecnico di Milano" Technical University in 1998, discussing a thesis on
a CdZnTe cross-connect for optical networks.
Since 2000 he has been working in STMicroelectronics in the ESD protections
development team for Smart power technologies. He is now the team leader of
the group responsible for ESD protections development, latch-up immunity and
bipolar parasitic analysis in BCD Smart-Power technologies.
He co-authored several technical papers in ESD protections field.
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'Pulsed Characterization in the ESD Domain'
by Evan Grund
In the ESD time domain from picoseconds to several hundred nanoseconds,
various stress pulses are commonly used to characterize devices and
circuits. The standardized ESD stress test pulses used today will be
compared by examining the data they provide and the limitations of available
testing equipment. Changes that may occur to testing standards and the
emerging new standards will be presented. The capabilities and limitations
of today's pulse generators, ESD event simulators, and measurement equipment
will be reviewed. New IC technologies and their applications drive new
specifications and allow predictions of new test capabilities that may be in
our future.
Evan Grund is the director of a new test and measurement company, Grund
Technical Solutions, located in San Jose California. Evan was formerly VP
of Oryx Instruments, now part of Thermo Fisher Scientific, where he was the
developer of their Celestron family of TLP products. Over the last six
years Evan has designed a variety of TLP/ESD equipment, including the
development of high impedance TDRT, VF-TLP with Kelvin probes, combined
TLP-HBM systems, and TLP probe card systems. Evan began his career as an
instrumentation engineer designing nanosecond pulse amplifiers and
picosecond timing systems at the Stanford Linear Accelerator Center while
completing his MSEE at Stanford University. Prior to joining Oryx/Thermo
Fisher, Evan served as an engineering department manager for many Silicon
Valley companies, including KLA-Tencor, Lam Research and Novellus Systems.
He has patents issued in the fields of data processing, optical
measurements, high power control systems, and has several patents pending
for TLP and HBM systems. During the last five years, he has presented 15
papers and tutorials at ESD Symposia, Forums, and Workshops including the
first IEW. Evan is an active member of the ESD Association Working Groups
on Device Testing Standards.
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'Advanced Failure Analysis with respect to ESD Failures'
by Philipe Perdu
Failure Analysis (FA) is a key activity in numerous integrated circuit
related problems. The purpose of FA is to diagnose the failure (electrical
diagnosis) and then to locate it (defect localization) in order to perform
the Physical Analysis. But the output is not only to print technical reports
on the failure itself. It has to determine the root cause. This knowledge is
mandatory to suggest improvements and to limit further problems. EOS and ESD
damages are the main cause of failures at chip level and in this case, FA
has to determine the failure mode. The knowledge of the electrical stress
that can reproduce the same electrical and physical signature and the
compliance with product history is one of the main challenge to perform an
useful field return FA. After an overview of FA process we will underline
the specificities of FA in case of EOS / ESD suspicion.
Philippe Perdu is Senior Expert in microelectronics at CNES. He has led the
IC Failure Analysis at CNES laboratories (French national space agency)
since 1988. Prior to this, he developed electronic systems for telephone,
automotive part, and military system manufacturers. He holds an Electronic
Specialty MS and Ph.D. from the National Academy of Arts and Trades (1988)
and the Paul Sabatier University (1994) respectively and HDR (academic
research supervisor) at Bordeaux University in 2001. In addition to his
operational tasks, he has been active in the research and development of
tools and methods for VLSI failure analysis. He has authored or co-authored
more than 120 papers and 12 patents. He is chairman of CCT MCE, a corporate
network on electronic components and MEMS, president of ANADEF, the French
FA society, board member of EDFAS (Electron Device Failure Analysis Society)
and EUFANET (European Failure Analysis NETwork).
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