Chairman: Guido Notermans, ST-Ericsson

The technical program consists of a discussion of peer-reviewed posters in three sessions. You may expect a wide range of current ESD subjects, ranging from hot topics like CDM and system level testing, to mysterious HBM fails, and new GaAs protection devices. The presentations are preceded by a brief podium introduction by each author. These presentations can be used by the workshop participants to select the posters for discussion.

Technical Session A
A.1 - Transient Latch-up in Large NFET Switch Arrays
Nathaniel Peachey, RFMD; Rick Phelps, IBM
Power management circuits often employ large switching arrays to provide a stable voltage output. The displacement currents can be large enough to trigger snapback during operation and the NMOS array can latch on and sustain damage. A particular example of this type of transient latch-up phenomena is described.

A.2 - ESD Induced Latch-Up Case and Prevention Measures
Andy Noiret, Micronas
The poster presents a case of ESD stress induced latch-up found in an late stage of an integrated circuit development. The Failure Analysis led to more robust layout design rules in the mixed signal high voltage technology C45 (0.45μm).

A.3 - About the ESD Sensitivity Classification According to HBM
Tilo Brodbeck, Adrien Ille, Wolfgang Stadler, Jan Weigmann, Infineon Technologies AG, Intel Mobile Communication
The limits of HBM device classification will be investigated. The present HBM standard cannot guarantee clear results without ambiguity regarding the pin-combination sets, the HBM classification procedure, and the coverage of the statistical aspect of the failing modes.

A.4 - Design and Performance of GaAs Schottky Diodes for On-Chip IC Device ESD Protection
Frank Gao, David Whitefield, David Petzold, Dylan Bartle, Skyworks Solutions
GaAs devices are typically used when there is an RF performance advantage over standard silicon processes. Traditional ESD protection methods degrade RF performance and are often not used. Therefore, few characterization data are available. In this work, GaAs FETs and capacitors have been characterized, and an array of ESD protection diodes were analyzed.

A.5 - Improving IBIS for System Level ESD Simulation
Fabrice Caignet, Nicolas Monnereau, Nicolas Nolhier, David Trémouilles, Marise Bafleur, LAAS-CNRS
An extended and improved IBIS model is presented. Including information extracted from TLP measurements that allow Equipment Manufacturers to predict the ESD performance of their circuit by accurate simulations during the design phase, and yet protect the intellectual property of semiconductor manufacturers.

A.6 - Design Considerations to Reduce Process
Sensitivity for Transient-Triggered Active Rail Clamps in Advanced CMOS Technologies
Sunitha Venkataraman, Cynthia Torres, David Catlett, Tim Rost, Chris Barr, Keith Burgess, Texas Instruments
As technologies advance, transient-triggered active MOSFET rail clamps can be more sensitive, not only to age related effects but also to process variations. This work offers a case study in the use of existing industry simulation tools to optimize ESD trigger circuits to make them less sensitive to parameter shifts due to aging and process variation.

Technical Session B
B.1 - Full TLP/vf-TLP Characterization of ESD Network Protection Based on Beta-Matrix Concept
Johan Bourgeat, Philippe Galy, Jean Jimenez, David Marin-Cudraz, STMicroelectronics
A Beta-Matrix is a new concept which integrates six SCRs in a common structure using a single triggering gate. This work introduces a trigger circuit able to turn on one of SCRs depending on which pins are stressed with which polarity, in a 32nm high-k metal-gate CMOS technology.

B.2 - Impact of Tester Source Impedance on HBM Failure Level
M. Scholz, S.-H. Chen, D. Linten, S. Thijs, M. Sawada, D. Johnsson, G. Groeseneken, imec, Vrije Universiteit Brussels, Katholieke Universiteit Leuven, HANWA, HPPI
The same device under test is stressed with a HBM tester and a so called HBM-500 ESD tester. Although the current waveforms into a short are very similar, the different source impedances and discharge circuits cause a clear miscorrelation when connecting a device under test.

B.3 - Low Pin-Count Unexplained HBM Cumulative Effect
Andrea Boroni, Lorenzo Cerati, Leonardo Di Biccari, Gianluca D'Alesio, Fabio Quintana, Alberto Mena Hernandez, Laura Solevi, STMicroelectronics
The number of false failures in ESD qualification due to testing and IC parasitics is growing. This work presents an investigation of spurious cumulative effects due to zap on different pins, even when stressing a very limited number of pads.

B.4 - Bipolar ESD Structures for the System Level Timeframe
Jean-Philippe Laine, Patrice Besse, Alain Salles, Freescale Semiconductor
ESD system level requirements imply design efforts to achieve fast and robust ESD structures. Several active bipolar ESD structures are tested with TLP measurement from 20ns up to 1us. Results show how its robustness depends on the concept configuration. A trade-off between size and concept is found.

B.5 - Low Voltage Diodes Metal Layout Optimization to Sustain System Level ESD Current Stress
Leonardo Di Biccari, Lorenzo Cerati, STMicroelectronics
The high current densities required by system level ESD standards are becoming difficult to reach in new Smart-Power technologies due to the use of thin metals. In this work a metal layout optimization using R3D simulations is presented to increase the current capability of ESD diodes in BCD8 technology.

B.6 - An SCR Clamp with a Dual-base ESD Detection Driver
A.A. Shibkov, V.A. Vashchenko, Angstrom, Maxim
A novel small footprint, low voltage, SCR clamp is proposed and validated using mixed-mode numerical simulations. The clamp combines a transient voltage detection circuit to control a dual-base triggered SCR.

Technical Session C
C.1 - ESD Solution for NC Pin of a Smart Card IC
Chang-Su Kim, Jae-Hyok Ko, Sung-Pil Jang, Kyoung-Soon Cho,
Han-Gu Kim, Samsung
An ESD protection methodology for NC pins on smart card ICs is discussed. The failure mechanism is analyzed through discharge waveform measurement for a regular I/O pin during an ESD event at a neighboring NC pin. In addition, on- and off-chip ESD solutions are proposed.

C.2 - Utilizing a Keep-Out Zone of Through Silicon Vias for ESD Protection Devices in 3D Stacked ICs
Shih-Hung Chen, Steven Thijs, Dimitri Linten, Guido Groeseneken, imec
3D stacking of ICs connected with Through-Silicon-Vias (TSV) is a promising candidate for real systems-on-chip applications. However, mechanical strain induced by the TSV can impact MOSFET Vth and mobility. Therefore, a Keep-Out Zone (KOZ) is defined, which implies that active devices are forbidden in this area. This paper investigates the placement of ESD protection devices inside this KOZ.

C.3 - Pitfalls When Using the SEED Methodology
M. Scholz, S.-H. Chen, D. Linten, S. Thijs, M. Sawada,
G. Groeseneken, imec, Vrije Universiteit Brussels, Katholieke Universiteit Leuven, HANWA
The SEED methodology is applied for comparison of two ESD protection clamps under system level ESD stress. It is shown that SEED cannot be used as a general design methodology. Instead the transient interaction between on-chip and off-chip ESD protection needs to be carefully studied to prevent an unexpected failure of the on-chip ESD protection during system level ESD stress.

C.4 - Contributions to the Variation of HMM Test Results
Richard Derikx, Theo Smedes, Rudolf Velghe, Maarten Swanenberg, NXP Semiconductors
An ESD gun test setup, including PCB/socket design and package selection, is presented. ESD tests with this setup give stable results although case studies demonstrate that small details may have significant effect on the results. Improvement of the setup is presented, by characterization of the effects of certain parameters.

C.5 - Understanding vf-TLP and TLP Stress-Induced Failure Mechanisms of ESD Devices in a 28nm Bulk CMOS Technology
Rahul Mishra, Junjun Li, James Di Sarro, Robert Gauthier, IBM
Physical failure analysis of 28nm bulk ESD devices shows different failure mechanisms depending on device design parameters and TLP testing type. The devices being studied are n+/pw diode and ESD silicide-blocked nMOSFET. It is shown that failure mode changes when devices are stressed with vf-TLP pulses. Two unexpected failure modes are uncovered in this paper.

C6 - A Study of the TLP Voltage-Step Dependency of It2 in a 16V DDDMOS Process
Chia-Tsen Dai, Po-Yen Chiu, Ming-Dou Ker, Fu-Yi Tsai, Yan-Hua Pan, Chia-Ku Tsai, National Chiao-Tung University, Faraday Technology Corporation
In this work, the measured results of TLP tests of a traditional RC-triggered ESD clamp have different It2 levels when using different voltage steps in the TLP tester. Thus, in order to get a reasonable It2 result, the voltage-step dependency should be taken into consideration, especially in HV CMOS processes.