Seminars give an overview of technology challanges!

Seminar Chair:
Horst Gieser (FhG EMFT)

This year's seminars provide a concise and up to date overview on five complex key themes of the IEW 2012. Three of them are focused on assessing, differentiating, and mitigating the risk of ESD weakness at the device level from system level issues and cases of EOS, which turn out to be the majority of customer complaints. Concise failure analysis is key to understanding the root cause and guiding the effort for failure reproduction in a laboratory. In view of SoC this analysis becomes more and more difficult as feature sizes are shrinking to below tens of nanometers, metallization layers increase, and picosecond variations count, and even worse, several dies will be stacked into 3D systems.One seminar introduces the art of designing robust ESD protection for analog and high voltage technologies to be operated in harsh environments. Another seminar provides a view up the scaling path into the world of multigated FinFETs and their ESD protection. The last seminar will discuss how to bridge the gap between an IC Design and its application in view of ESD and EMC.

Seminar 1
Electrical Overstress (EOS) of Automotive Semiconductors -- Root Causes and Conclusions
Christoph Thienel, Robert Bosch GmbH

Summary:
Electrical Overstress (EOS) is one of the last not yet fully understood root causes for failing semiconductors in the automotive area. It often is misleadingly mixed up with Electrostatic Discharge (ESD). Sometimes it is wrongly assumed EOS may be caused by a weak design or a weak technology. On the contrary it is a very common out of spec operation mode, which may destroy semiconductors. In the vast majority of cases there is no ESD event ahead of EOS pulse. Normally it is difficult to clarify the root causes, but often EOS simply is caused by mechanical reasons or plugging under voltage (hot plugging). So, EOS should be investigated and cared about much more.

Seminar 2
EOS / ESD Related Product Failure Analysis
Peter Egger, Infineon Technologies AG

Summary:
Physical root cause finding is an essential part in understanding the behavior of failing products and the development of appropriate countermeasures. Especially in advanced technologies with up to 12 metal layers and structure sizes below the spacial resolution of FA tools, product failure analysis on ESD or EOS fails is no longer a simple task. This seminar will give a brief overview about standard tools used for global fault isolation (lock-in IR thermography, emission microscopy, laser based techniques), their advantages and limitations. Dependent on the structure size of the product and failure mode, these techniques cannot provide the exact localization of the fail. Additional methods on transistor level (micro- and nano- probing) are necessary to generate a reliable failure hypothesis for successful physical preparation. Case studies will be presented covering unusual failure modes and 'non visual defects' caused by ESD stress. Finally ESD versus EOS aspects are discussed, as well as the FA contribution on these issues.

Seminar 3
ESD Protection in FinFET Technologies
Steven Thijs, imec

Summary:
FinFET technology is widely accepted as being one of the main candidates to continue device scaling according to Moore's law beyond the 16 nm node. FinFET devices indeed have superior scalability and very good channel control. FinFETs can be processed both on Silicon-On-Insulator (SOI) or on bulk substrates. Last year, Intel announced first mass production of Bulk-FinFET for their 22 nm processors. This seminar presents an overview of 6 years of ESD research on both SOI- and Bulk-FinFET technology. Basic ESD protection devices are investigated and the influence of FinFET specific parameters is highlighted.

Seminar 4
ESD Design in High Voltage Technologies
Joost Willemen, Infineon Technologies AG;
Lorenzo Cerati, STMicroelectronics

Summary:
This seminar gives an introduction to ESD design in high voltage technologies for integrated circuits with pin voltages from 12V upwards. After a short introduction of typical applications and requirements, an overview of different technologies and the typical device portfolios in these technologies will be given. Different ESD protection concepts are introduced, analyzing advantages and disadvantages of the various possible approaches to implement ESD networks (diodes, snapback, active clamps…). Finally, HV-technology and design related challenges regarding ESD protection are discussed, with a special focus on parasitic bipolar formation and their impact on device performance.

Seminar 5
Bridging the Gap Between IC Design and its Application
Mart Coenen, EMCMCC

Summary:
IC ESD protection measures need to combine the handling constraints effectively without causing any functional drawback to its foreseen application. With today's nanometer processes, the vulnerability of the circuits to be protected increases, though on the opposite side the RF immunity requirements, are enhanced for the so called 'global' pins at the application level. Questions need to be answered on what can and has to be done at the application, in the package and on-silicon to close this gap efficiently while being able to demonstrate compliance to the ESD standards applicable at the various verification levels concerned.