6th Annual International Electrostatic Discharge Workshop
2012 Schedule

Monday, May 14, 2012 REGISTRATION AND CHECK-IN

12:00 PM-6:00 PM Registration: Pick up badges and handouts.
12:00 PM-10:00 PM Hotel check-in: Get room assignment & room key.
Monday, May 14, 2012
1:30 PM-2:50 PM Seminar 1:
  Electrical Overstress (EOS) of Automotive Semiconductors - Root Causes and Conclusions
Christoph Thienel, Robert Bosch GmbH
2:50 PM-4:10 PM Seminar 2:
  EOS / ESD Related Product Failure Analysis
Peter Egger, Infineon Technologies AG
4:10 PM-4:40 PM Break
4:40 PM-6:00 PM Seminar 3:
  ESD Protection in FinFET Technologies
Steven Thijs, imec
6:00 PM-7:30 PM Dinner
7:30 PM-8:30 PM Evening Talk:
  The Biotechnological Art of Beer Creation
Tuesday, May 15, 2012
8:00 AM-8:10 AM Welcome - Technical Program Introduction
8:10 AM-9:05 AM Keynote:
  Game Changing Technologies in Health Care
Jo De Boeck, imec
9:05 AM-9:50 AM Invited Talk #1:
  Advancing CMOS Beyond the Si Roadmap: Chronicle of a
(R)evolution Foretold
Marc Heyns, imec, Katholieke Universiteit Leuven
9:50 AM-10:10 AM Break
10:10 AM-11:00 AM Technical Session A:
  A.1 - Transient Latch-Up in Large NFET Switch Arrays
Nathaniel Peachey, RFMD; Rick Phelps, IBM
A.2 - ESD Induced Latch-Up Case and Prevention Measures
Andy Noiret, Micronas
A.3 - About the ESD Sensitivity Classification According to HBM
Tilo Brodbeck, Adrien Ille, Wolfgang Stadler, Jan Weigmann, Infineon Technologies AG, Intel Mobile Communication
A.4 - Design and Performance of GaAs Schottky Diodes for On-Chip IC Device ESD Protection
Frank Gao, David Whitefield, David Petzold, Dylan Bartle, Skyworks Solutions
A.5 - Improving IBIS for System Level ESD Simulation
Fabrice Caignet, Nicolas Monnereau, Nicolas Nolhier, David Trémouilles, Marise Bafleur, LAAS-CNRS
A.6 - Design Considerations to Reduce Process Sensitivity for Transient-Triggered Active Rail Clamps in Advanced CMOS Technologies
Sunitha Venkataraman, Cynthia Torres, David Catlett, Tim Rost, Chris Barr, and Keith Burgess, Texas Instruments
11:00 AM-12:00 PM Poster Discussion Session A
12:00 PM-1:30 PM Lunch
1:30 PM-1:35 PM Announcements
1:35 PM-2:20 PM Invited Talk #2:
  Smart Power Technology on SOI
Piet Wessels, NXP Semiconductors
2:20 PM-3:05 PM Invited Talk #3:
  ESDA Advanced Topic Ad-hoc Working Group on Electrical Overstress (EOS)
Jean-Luc Lefebvre, Presto Engineering
3:05 PM-3:25 PM Break
3:25 PM-4:15 PM Technical Session B:
  B.1 - Full TLP/vf-TLP Characterization of ESD Network Protection Based on Beta-Matrix Concept
Johan Bourgeat, Philippe Galy, Jean Jimenez, David Marin-Cudraz, STMicroelectronics
B.2 - Impact of Tester Source Impedance on HBM Failure Level
M. Scholz, S.-H. Chen, D. Linten, S. Thijs, M. Sawada, D. Johnsson, G. Groeseneken, imec, Vrije Universiteit Brussels, Katholieke Universiteit Leuven, HANWA, HPPI
B.3 - Low Pin-Count Unexplained HBM Cumulative Effect
Andrea Boroni, Lorenzo Cerati, Leonardo Di Biccari, Gianluca D'Alesio, Fabio Quintana, Alberto Mena Hernandez, Laura Solevi, STMicroelectronics
B.4 - Bipolar ESD Structures for the System Level Timeframe
Jean-Philippe Laine, Patrice Besse, Alain Salles, Freescale Semiconductor
B.5 - Low Voltage Diodes Metal Layout Optimization to Sustain System Level ESD Current Stress
Leonardo Di Biccari, Lorenzo Cerati, STMicroelectronics
B.6 - An SCR Clamp with a Dual-base ESD Detection Driver
A.A. Shibkov, V.A. Vashchenko, Angstrom, Maxim
4:15 PM-5:30 PM Poster Discussion Session B
5:30 PM-7:00 PM Dinner
7:00 PM-8:00 PM Discussion Group Session A: Parallel Groups
  DG A.1 - The First Thing Industry Needs is a Test Standard for EOS Besides ESD and Latch-Up
DG A.2 - ESD Thresholds and Actual Risk of Failure
DG A.3 - System Level ESD
DG A.4 - The ESD Designer's Dilemma; Do We Design to Pass ESD Qualification or Real World EOS/ESD Events?
8:00 PM-9:00 PM Special Interest Group Session A: Parallel Groups
  SIG A.1 - ESD Data Analysis Tools
SIG A.2 - Transient Latch-Up (TLU)
SIG A.3 - ESD Parameters for ESD EDA Flow
Wednesday, May 16, 2012
8:00 AM-8:05 AM Announcements
8:05 AM-8:35 AM Reports on DG & SIG Session A
8:35 AM-9:55 AM Seminar 4:
  ESD Design in High Voltage Technologies
Joost Willemen, Infineon Technologies AG; Lorenzo Cerati, STMicroelectronics
9:55 AM-10:10 AM Group Picture
10:10 AM-10:40 AM Break
10:40 AM-12:00 PM Seminar 5:
  Bridging the Gap Between IC Design and its Application
Mart Coenen, EMCMCC
12:00 PM-1:00 PM Lunch
1:00 PM-5:30 PM Free Time
5:30 PM-7:00 PM Dinner
7:00 PM-8:00 PM Discussion Group Session B: Parallel Groups
  DG B.1 - The Industry Should Focus on ESD Control Since all Measures Taken there are More Effective and Cheaper than Design Solutions
DG B.2 - ESD Testing: Is it Time for a Revolutionary Change in Test Methods/testers, Rather than Small Evolutions?
DG B.3 - Everything You Always Wanted to Know About the Secrets of a Successful Cooperation Between Academia and Industry
DG B.4 - ESD Verification Tools: Will We Get to Push-button Solutions?
8:00 PM-9:00 PM Special Interest Group Session B: Parallel Groups
  SIG B.1 - Non-ESD Requirements That are Relevant for ESD Protection
SIG B.2 - Electrical Overstress
SIG B.3 - Charged Board Event
Thursday, May 17, 2012
8:00 AM-8:05 AM Announcements
8:05 AM-8:35 AM Reports on DG & SIG Sessions B
8:35 AM-8:55 AM Industry Council Report
8:55 AM-9:40 AM Invited Talk 4:
  System Level EMC/ESD Design – Challenges and Opportunities
Pasi Tamminen, NOKIA Corporation
9:40 AM-9:55 AM Break
9:55 AM-10:45 AM Technical Session C:
  C.1 - ESD Solution for NC Pin of a Smart Card IC
Chang-Su Kim, Jae-Hyok Ko, Sung-Pil Jang, Kyoung-Soon Cho, Han-Gu Kim, Samsung
C.2 - Utilizing a Keep-Out Zone of Through Silicon Vias for ESD Protection Devices in 3D Stacked ICs
Shih-Hung Chen, Steven Thijs, Dimitri Linten, Guido Groeseneken, imec
C.3 - Pitfalls When Using the SEED Methodology
M. Scholz, S.-H. Chen, D. Linten, S. Thijs, M. Sawada, G. Groeseneken, imec, Vrije Universiteit Brussels, Katholieke Universiteit Leuven, HANWA
C.4 - Contributions to the Variation of HMM Test Results
Richard Derikx, Theo Smedes, Rudolf Velghe, Maarten Swanenberg, NXP Semiconductors
C.5 - Understanding vf-TLP and TLP Stress-Induced Failure Mechanisms of ESD Devices in a 28nm Bulk CMOS Technology
Rahul Mishra, Junjun Li, James Di Sarro, Robert Gauthier, IBM
C.6 - A Study of the TLP Voltage-step Dependency of It2 in a 16V DDDMOS Process
Chia-Tsen Dai, Po-Yen Chiu, Ming-Dou Ker, Fu-Yi Tsai, Yan-Hua Pan, Chia-Ku Tsai, National Chiao-Tung University, Faraday Technology Corporation
10:45 AM-10:55 AM 2013 Announcements and Closing
10:55 AM-12:00 PM Poster Discussion Session C
12:00 PM-1:00 PM Lunch

The Industry Council is an independent Institution focused on target levels of ESD component testing, applying the HBM, MM and CDM standards. Roadmap LIFB

Revised: 1/24/2012 © Copyright, 1999-2012

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