Discussion Groups Chair: Theo Smedes (NXP)
The Tuesday and Wednesday evening discussion groups are an integral part of the workshop. Four parallel discussion groups are offered each evening. Each discussion group is assigned one or more moderators who have extensive expertise with the topic and will help to guide the discussion. However, the actual discussion depends on those participating in each group. Everyone is encouraged to bring along data and ideas to share that are of particular interest. As the workshop approaches, please check the IEW web site for updates from the discussion group moderators. You are also encouraged to send questions to the moderator before the workshop.
Discussion Group A.1
The First Thing Industry Needs is a Test Standard for EOS Besides ESD and Latch-Up
Moderator: Jean Luc Lefebvre, Presto Engineering
jean-luc.lefebvre@presto-eng.com
EOS currently is a loosely defined category of electrical stress. Does EOS relate to a failure signature or the root cause of the failure? Do ESD and latch-up events form subsets of the whole range of EOS events? If so, what 'other EOS events' are there? Which part of the failures do these 'other EOS events' constitute? How is IC component robustness determined and guaranteed and how do absolute maximum rating (AMR) levels relate to this? Would a test standard method for EOS, in addition to those for ESD and Latch-up, help to improve robustness levels of ICs, components and boards? This should be an excellent meeting to share your EOS, besides ESD and Latch-up, experiences in quality and reliability test scope.
Discussion Group A.2
ESD Thresholds and Actual Risk of Failure
Moderator: Terry Welsher, Dangelmayer Associates
terry@dangelmayer.com
How can we change the current way of working to include statistics of ESD events and product failure? HBM and CDM ESD thresholds have been useful as "figures of merit" to drive improvements in protection circuits. However, the relationship of these thresholds to actual quality or reliability risks is not well-understood. Many users believe that the risk of failure rises dramatically when the threshold falls even a small amount below the usual threshold requirements. This discussion group will explore better ways of communicating the risk of failure to users, better measures of ESD robustness than the simple threshold value and whether it is possible to characterize an ESD manufacturing process based on measurements (auditing).
Discussion Group A.3
System Level ESD
Moderator: Fabrice Caignet, LAAS-CNRS
fcaignet@laas.fr
ESD system level prediction has become a challenging issue for both IC suppliers and Equipment Manufacturers (EMs). Do you think that ESD protections can be described with only a few parameters? Do you think that IC suppliers can use a shared model to ensure that ICs can handle system level ESD events? Can such a model help the EMs to optimize their systems? Can such models be exchanged between suppliers and EMs? The question of the relevant parameters for system level simulation that can be used by suppliers and/or EMs will be addressed at this meeting.
Discussion Group A.4
The ESD Designer's Dilemma: Do We Design to Pass ESD Qualification or Real World EOS/ESD Events?
Moderator: James W. Miller, Freescale Semiconductor
rvkg60@freescale.com
ESD qualification success on IC products is often determined based solely on performance to the industry standard component level HBM/CDM stress tests. But the stress events which the HBM/CDM simulators attempt to reproduce represents only a small part of the range of real-world powered and un-powered EOS/ESD stress events a component IC may suffer during system level manufacturing and in the field. System level EOS, cable discharge and gun-stress events, for example, have been widely reported as common causes of IC damage, and may represent a higher risk to ICs than HBM/CDM events. But, since ESD qualification is typically not gated by tests for these real-world events, should ESD designers continue to focus primarily on HBM/CDM? How relevant is HBM/CDM testing today? What types of EOS/ESD fails are you seeing on products today? Are you including tests for these failure modes in your qualification plans? Moving forward, how do we define an appropriate set of powered and un-powered EOS/ESD stress events for qualification? On the other side: ESD Simulators have been reported to suffer from artifacts: non-ideal HBM waveforms may cause 'unwanted' fails. Is it a pitfall to design for being able to pass ideal stresses? How does that relate to the much less predictable real ESD threats?
Discussion Group B.1
The Industry Should Focus on ESD Control Since all Measures Taken There are More Effective and
Cheaper Than Design Solutions
Moderator: Yorgos Christoforou, NXP Semiconductors
yorgos.christoforou@nxp.com
How much of the EOS/ESD issues in your industry can be solved by (a) improving EOS/ESD robustness of the designs or (b) removing, through better control, the EOS/ESD root cause or latent failures? This is the topic of this discussion. Several questions can be addressed: Which control methods do you use in your industry? Which design methods do you use in your industry? What is the Return-on-Investment for each approach? Have you encountered cases where weak products can have an excellent performance in the final product thanks to robust control techniques? Do you think the two approaches correlate (e.g. more design needs less control and vice versa)? Does the choice of the approach depend on the type of the market/industry addressed? What is the preferred approach of the management in your industry? Will the industry direction, with respect to this topic, have to change in the future with the development of new technologies? The flow of the discussion will mainly depend on your participation.
Discussion Group B.2
ESD Testing: Is it Time for a Revolutionary Change in Test Methods/Testers, Rather than Small Evolutions?
Moderator: Tom Meuse, Thermo Fisher Scientific
tom.meuse@thermofisher.com
ESD testing, being device level or system level, HBM, CDM or the now "obsolete" MM test methods have evolved over the years to
incorporate knowledge gained from continued use of the present standards. Testers have also evolved to incorporate changes made to the standards or to eliminate findings during usage, such as the Trailing Pulse phenomena. The question today is: do we need to rethink ESD testing all together? CDM testing may take another direction, away from field induced testing, to allow testing of smaller devices and to improve testing repeatability. Should HBM and System Level (or HMM) move away from today's testing requirements? And if so, what are your suggestions?
Discussion Group B.3
Everything You Always Wanted to Know About the Secrets of a Successful Cooperation Between Academia and Industry
Moderators: Marise Bafleur, LAAS-CNRS; Patrice Besse, Freescale Semiconductor
marise@laas.fr • pbes01@freescale.com
There are many barriers (cultural, institutional, operational) that could make cooperation between academia and industry partners difficult. However, overcoming these barriers can result in a fruitful cross-fertilization that can lead to innovation. In the field of EOS/ESD, over the last ten years, more and more papers presented at the IEW and EOS/ESD Symposium are issued from academia-industry cooperative projects. We invite you to share your experience in bridging these cultural gaps and also discuss problems that are still pending. We will open the discussion with the example of a sustainable partnering in the field of ESD between LAAS-CNRS and Freescale Semiconductor.
Discussion Group B.4
ESD Verification Tools: Will We Get to
Push-Button Solutions?
Moderator: Matthew Hogan, Mentor Graphics
matthew_hogan@mentor.com
There has been a surge in development of newly designed EDA verification tools over the past few years. For ESD applications, much of the previous best practices included visual inspection, home-grown tools, SPICE simulations and flows that were put together using traditional DRC, LVS and ERC solutions. Designers expect ESD verification tools to provide a push button use model where the result provides a clear indication of where a certain rule has violated the constraint, and how this should be fixed. Much like how DRC checks operate today, the designer then makes the change, re-runs the design and repeats until all violations are removed. Can this goal be achieved for general purpose ESD verification tools as well? Or should we accept that ESD verification tools cannot be made as general as DRC verification tools? What level of use model and debugging is suitable? The same as DRC? LVS? Or something else? Are the expectations for topological and layout checks different? Is it inevitable that results need interpretation? That checks which are tailored for the design styles of one company require modification for a different design style at another? Can all aspects of an ESD network be checked by software? What is your experience in practice, when using currently available tools? This should be an excellent meeting to share your lessons learned and pick up ideas for improved ESD design verification at your company and/or insights to improved ESD verification software offered by EDA vendors.
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